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Product Detailed Parameters
- Description：IC FF JK TYPE DUAL 1BIT 16DIP
- Series：74HCT
- Mfr：Harris Corporation
- Package：Tube
- Function：Set(Preset) and Reset
- Type：JK Type
- Output Type：Complementary
- Number of Elements：2
- Number of Bits per Element：1
- Clock Frequency：60 MHz
- Max Propagation Delay @ V, Max CL：35ns @ 4.5V, 50pF
- Trigger Type：Negative Edge
- Current - Output High, Low：4mA, 4mA
- Voltage - Supply：4.5V ~ 5.5V
- Current - Quiescent (Iq)：4 µA
- Operating Temperature：-55°C ~ 125°C (TA)
- Mounting Type：Through Hole
- Supplier Device Package：16-PDIP
- Package / Case：16-DIP (0.300", 7.62mm)
- Input Capacitance：10 pF
- Grade：-
- Qualification：-
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Overview
The CD74HCT112E is a dual JK flip-flop integrated circuit belonging to the HCT logic series. It features two independent JK flip-flops with negative-edge triggered clock inputs and active-low preset and clear inputs. The device utilizes CMOS technology, operates within a supply voltage range of 4.5V to 5.5V, and provides true and complement outputs for each flip-flop. It is housed in a 16-pin DIP package and supports operation across an extended temperature range.
Feature Summary
- Dual independent JK flip-flops with complementary outputs
- Negative-edge triggered clocking mechanism
- Active-low asynchronous preset and clear controls
Applications
- Digital state storage circuits
- Frequency division networks
- Shift register construction
Procurement Notes
Verify the manufacturer origin carefully, as Harris Corporation assets were acquired by Texas Instruments. Ensure the specific suffix 'E' corresponds to the correct 16-pin DIP package variant. Confirm RoHS compliance status relative to the production batch, as older Harris-manufactured units may differ from current TI equivalents.
Selection Notes
Select this component when dual JK functionality with TTL-compatible input levels is required. The HCT series ensures compatibility with standard TTL logic families while offering CMOS power advantages. Verify that the negative-edge triggering aligns with the system clock timing requirements compared to positive-edge alternatives.
Part Context
This part belongs to the widely adopted 74HCT logic family, designed for high-speed digital applications requiring interface between CMOS and TTL systems. The CD74HCT112 specifically addresses designs needing multiple bistable elements within a single package, simplifying board layout for sequential logic implementations.
Replacement Considerations
CD74HC112N
FAQ
What is the trigger type for the clock input?
The clock inputs are negative-edge triggered.
How many flip-flops are contained in this package?
The device contains two independent JK flip-flops.
