CDCL1810ARGZT

Overview

The CDCL1810ARGZT is a high-performance clock buffer and divider manufactured by Texas Instruments. It features one differential LVDS input and ten differential CML outputs, supporting frequencies up to 650 MHz. The device operates on a single 1.7V to 1.9V supply with a typical power consumption of 410 mW. It provides low input-to-output added jitter of 10 fs RMS. The component is housed in a 48-pin VQFN (RGZ) package with an exposed pad, designed for surface mount applications within an industrial temperature range of -40°C to +85°C.

Feature Summary

• Low Jitter Performance: Input-to-output added jitter is specified at 10 fs RMS.
• Flexible Frequency Division: Supports programmable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80 via two independent groups.
• Phase Adjustment: Output groups allow phase adjustment steps based on the division ratio, calculated as ΔΦ = 1/(n × Fout).
• Serial Control: All device settings are configurable via a 1.8V SDA/SCL serial interface.

Applications

• High-speed data communication systems requiring precise clock distribution.
• Test and measurement equipment needing low-jitter clock signals.
• Industrial control systems operating in harsh environments (-40°C to +85°C).

Procurement Notes

Verify the package type matches the 48-VQFN (RGZ) specification. Confirm the operating voltage range aligns with the 1.7V to 1.9V requirement. Ensure the application supports the 1.8V limit on the serial interface. Check that the thermal design accommodates the 410 mW typical power dissipation.

Selection Notes

Select this component when a single LVDS source must drive multiple CML loads with minimal jitter. The 10-output configuration allows driving separate subsystems from one clock source. Consider the 650 MHz maximum frequency limit against system requirements. Verify compatibility with AC coupling if connecting to LVDS receivers.

Part Context

This part belongs to the CDCL1810 series of clock buffers. It serves as a fanout buffer and divider, converting a single differential input into ten synchronized outputs. The RGZ suffix indicates the 48-lead VQFN package variant.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Evaluate other TI clock buffer families for pin-compatible alternatives if necessary.

FAQ

What is the maximum operating frequency?

The CDCL1810ARGZT supports a maximum frequency of 650 MHz for both its LVDS input and CML outputs.

How is the output frequency determined?

The output frequency is derived from the input frequency divided by a programmable ratio P (Fout = Fin/P), where P can be 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, or 80.

Is the serial interface compatible with standard logic levels?

No, the SDA/SCL serial interface is limited to 1.8V tolerance.