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The CS493105-CLZR is a member of the Cirrus Logic CS493XX family, specifically designated as a Broadcast Sub-family audio decoder. It functions as a multi-standard audio DSP designed for broadcast applications. The component supports PES Layer decode for A/V sync and decodes Dolby Digital, MPEG-2, Advanced Audio Coding Algorithm (AAC), MPEG-1 (Layers 1, 2, 3) Stereo, and MPEG-2 (Layers 2, 3) Stereo. It features an 8-channel output capability with dual zone output support and dynamic channel remappability. The device handles up to 192 kHz Fs at 24-bit throughput and includes an SRAM interface for increased delay and buffer capability.
Verify the specific ordering suffix CLZR against the manufacturer's current datasheet to confirm package type and tape-and-reel specifications. Confirm RoHS compliance status and lead-free designation prior to procurement. Check for any end-of-life notifications or obsolescence warnings associated with this part number from official Cirrus Logic channels before finalizing supply chain agreements.
Select the CS493105-CLZR when designing broadcast-specific audio solutions requiring MPEG-1/2 stereo and Dolby Digital decoding. Ensure the system design accommodates the required external memory interfaces for firmware loading and data buffering. Verify that the host processor can support the necessary SPI, I2C, or parallel host communication modes defined in the control port specifications.
This component belongs to the CS49300 Family DSP, which supersedes the earlier CS4923 through CS4929 series. The CS493XX family is segmented into distinct sub-families tailored for DVD, Broadcast, and AVR markets. The CS4931X sub-family specifically targets broadcast applications, offering a subset of the full family's decoding capabilities optimized for digital transmission standards.
Direct replacements within the same family include other CS4931X variants such as CS49310, CS49311, and CS49312, depending on the specific required codec support. Cross-family replacement with the CS4923/4/5/6/7/8/9 series is possible but requires verification of pin compatibility and feature set reduction.