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CS5372-BSZ is listed in the ADCs/DACs - Special Purpose range at ChipApex. The manufacturer field lists Cirrus Logic Inc.. Its product description is IC MODULATOR 24BIT 512K 24SSOP. Review the specifications below when checking this part for your BOM.
The CS5372-BSZ is a two-channel, fourth-order delta-sigma modulator designed for high-resolution measurement applications. It features a clock-jitter-tolerant architecture and fully differential analog inputs capable of handling 5 Vpp signals. The device delivers a dynamic range of up to 127 dB SNR at a 215 Hz bandwidth with typical total harmonic distortion of -118 dB. Operating from a 2.048 MHz master clock, it generates an oversampled serial bit stream at 512 kbits per second. Power consumption is 25 mW per channel in normal mode and reduces to 15 mW per channel in low-power mode.
Verify the 'BS' suffix designation against current manufacturer documentation to confirm specific grade or testing variations. Confirm availability status as distribution data may indicate limited supply or end-of-life conditions for this component family.
Select the CS5372-BSZ for dual-channel requirements; use the CS5371 for single-channel configurations. Ensure compatibility with external digital filters such as the CS5376A or CS5378. Design input anti-alias filters with a -3 dB corner at 8 kHz for 2.048 MHz operation or 4 kHz for 1.024 MHz low-power mode.
The CS5372 is part of the CS5371/CS5372 family of low-power, high-performance modulators. While the CS5371 provides one channel, the CS5372 integrates two channels into a single 24-pin SSOP package. This integration supports multi-channel system designs, including 2-channel, 3-channel (with CS5371), and 4-channel (with two CS5372s) configurations.
Publicly confirmed substitute part numbers are not available in the provided source material. Evaluate the CS5371 for single-channel needs or verify if other Cirrus Logic modulators meet specific performance criteria.
The modulators tolerate a 5% over-range voltage. If the input exceeds full scale by more than 5%, the modulator may become unstable and collapse to a 1st order system until loop stability is restored.
A simple single-pole low-pass RC filter is recommended across the differential rough and fine analog inputs. For a 2.048 MHz MCLK, the -3 dB corner should be set to 8 kHz.
Idle tones can be eliminated by applying a differential DC offset to the inputs. Activating the OFST pin adds -50 mV of differential offset to push idle tones out of the measurement bandwidth.
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