CY37128P160-100AXC

Complex Programmable Logic Devices Overview

The CY37128P160-100AXC is a 5V Ultra37000 CPLD featuring 128 macrocells and up to 133 I/O pins in a 160-lead TQFP package. It operates at a maximum frequency of 100 MHz with a worst-case propagation delay of 10 ns. The device uses EEPROM storage for non-volatile configuration and supports In-System Reprogramming via JTAG. It includes four synchronous clocks, programmable bus-hold on all I/Os, and flexible clocking options.

Complex Programmable Logic Devices Feature Summary

• 128 Macrocells with 133 I/O pins
• 100 MHz speed bin (10 ns max tPD)
• EEPROM-based non-volatile storage
• JTAG-compliant ISR and Boundary Scan

Complex Programmable Logic Devices Applications

• PCI Local Bus interface designs
• High-density logic replacement
• In-system reprogrammable logic control

Complex Programmable Logic Devices Procurement Notes

Verify the specific suffix 'AXC' against official Infineon documentation to confirm lead-free status and commercial temperature range (-40°C to +85°C). Confirm availability as this component may be subject to discontinuation or limited supply constraints.

Complex Programmable Logic Devices Selection Notes

Select this part for applications requiring fixed pinout compatibility during design changes. Ensure VCCO is set to 5V for full PCI compliance. Verify that the 100 MHz speed grade meets system timing requirements compared to faster 167 MHz or slower 83 MHz variants.

Complex Programmable Logic Devices Part Context

Part of the Ultra37000 family offering consistent pinouts across densities. Designed for high routability with a Programmable Interconnect Matrix (PIM) that eliminates routing-dependent delays.

Complex Programmable Logic Devices Replacement Considerations

Check for CY37128VP160-100AXI (3.3V version) if voltage levels differ. Verify CY37128P160-83AXC for lower speed requirements.