CY7B991-2JC

Overview

The CY7B991-2JC is a Programmable Skew Clock Buffer (PSCB) from the RoboClock series, manufactured by Cypress Semiconductor. It features an integrated Phase-Locked Loop (PLL) and provides eight TTL outputs arranged in four user-controllable pairs. The device operates within a frequency range of 3.75 MHz to 80 MHz with a supply voltage of 4.5V to 5.5V. Key electrical specifications include output pair skew less than 100 ps typical (250 ps maximum), jitter under 200 ps peak-to-peak, and zero input-to-output delay. It supports selectable skew up to 18 ns, inverted/non-inverted outputs, and frequency division/multiplication functions.

Feature Summary

• Integrated PLL with selectable skew up to 18 ns and zero input-to-output delay
• Eight TTL outputs in four pairs, each driving terminated transmission lines as low as 50Ω
• Frequency operation from 3.75 MHz to 80 MHz with divide-by-two/four and multiply-by-two/four capabilities
• Low jitter specification (< 200 ps peak-to-peak) and < 100 ps typical matched-pair skew

Applications

• High-performance computer system clock distribution
• Zero-skew clock tree generation for multi-load systems
• Compensation for varying metal trace delays on printed circuit boards
• Board-to-board clock distribution networks

Procurement Notes

Verify the ordering suffix 'JC' corresponds to the J65 package type (32-Lead Plastic Leaded Chip Carrier) and Commercial operating temperature range (0°C to +70°C). Confirm that the specific speed grade '-2' aligns with the required 250 ps maximum skew performance. Ensure compatibility with 5V logic levels and TTL input/output requirements.

Selection Notes

Select this component when precise timing alignment between multiple clock domains is critical. The CY7B991-2JC is suitable for designs requiring programmable skew to compensate for PCB trace length differences. Choose this part over the CMOS CY7B992 variant if TTL logic levels are required for the output drivers. Verify that the application frequency falls within the 3.75–80 MHz range supported by the FS pin configuration.

Part Context

The CY7B991-2JC belongs to the CY7B991/CY7B992 family of Programmable Skew Clock Buffers. It is functionally identical to the CY7B992-2JC except for the output logic family; the CY7B991 provides TTL outputs while the CY7B992 provides CMOS outputs. Both share the same internal PLL architecture, pinout, and control logic.

Replacement Considerations

Public confirmed substitute part numbers: CY7B992-2JC (CMOS output version).

FAQ

How is the programmable skew range determined?

The skew range is defined by time units (tU) derived from the operating frequency and the FS pin setting. Outputs can be skewed up to ±6 time units from their nominal position, allowing for total skew adjustments of up to 18 ns.

What is the function of the TEST pin?

The TEST pin controls the internal PLL. When tied LOW (normal operation), the PLL synchronizes the REF and FB inputs. If forced to MID or HIGH states, the PLL disconnects, and REF input levels directly control all outputs.

Can the device operate as a clock multiplier?

Yes. By connecting a divided output (divide-by-two or divide-by-four) to the FB input, the internal PLL multiplies the reference frequency at the REF input by two or four at the undivided outputs.