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Product Detailed Parameters
- Description:IC SWITCH DPST-NOX2 45OHM 16SOIC
- Series:-
- Mfr:Vishay Siliconix
- Package:Tape & Reel (TR)
- Switch Circuit:DPST - NO
- Multiplexer/Demultiplexer Circuit:2:01
- On-State Resistance (Max):45Ohm
- Channel-to-Channel Matching (ΔRon):-
- Voltage - Supply, Single (V+):13V ~ 36V
- Voltage - Supply, Dual (V±):±7V ~ 22V
- Switch Time (Ton, Toff) (Max):150ns, 100ns
- -3db Bandwidth:-
- Charge Injection:60pC
- Channel Capacitance (CS(off), CD(off)):12pF, 12pF
- Current - Leakage (IS(off)) (Max):500pA
- Crosstalk:-90dB @ 1MHz
- Operating Temperature:-40°C ~ 85°C (TA)
- Mounting Type:Surface Mount
- Package / Case:16-SOIC (0.154", 3.90mm Width)
- Supplier Device Package:16-SOIC
- Number of Circuits:2
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Overview
The DG405DY-T1 is a low-power, high-speed CMOS analog switch manufactured by Vishay Siliconix. It features two single-pole double-throw (SPDT) switches in a 16-pin narrow SOIC package. The device supports a maximum supply voltage of 44 V and an analog signal range of ±15 V. Key electrical parameters include a typical on-resistance of 30 Ω, a maximum of 45 Ω at room temperature and 55 Ω across the full temperature range. Switching performance includes a typical turn-on time of 75 ns and a turn-off time of 30 ns. Leakage currents are specified at a maximum of 0.5 nA for channel off-leakage and 1 nA for channel on-leakage at room temperature. Power dissipation is rated at 600 mW.
Feature Summary
- Break-before-make switching action guaranteed for SPDT configurations to prevent signal shorting during transitions.
- Ultra-low power consumption with typical power dissipation of 0.35 µW, suitable for battery-operated applications.
- TTL and CMOS logic compatible for simple interfacing with standard digital control circuits.
- Epitaxial layer design prevents latch-up, ensuring reliable operation under high-voltage conditions.
Applications
- Audio and video signal routing
- Sample-and-hold circuits
- Battery-powered industrial systems
- Test equipment signal paths
- PBX and PABX communication lines
Procurement Notes
Verify component authenticity through authorized distributors or direct manufacturer channels. Confirm RoHS compliance status as indicated by the -E3 suffix if lead-free terminations are required. Check datasheet revision history for any updates to mechanical dimensions or electrical limits before finalizing procurement specifications.
Selection Notes
Select this component when break-before-make timing is critical for SPDT switching applications. Ensure the analog signal range does not exceed ±15 V to maintain optimal on-resistance flatness. Verify that the logic supply voltage aligns with TTL or CMOS standards for proper interface compatibility.
Part Context
The DG405DY-T1 belongs to the DG40x series of low-power analog switches from Vishay Siliconix. It shares the same package and general electrical characteristics as the DG401 and DG403 but differs in internal switch configuration. The DG401 contains two SPST switches, while the DG403 offers two DPST switches. This specific part number denotes the surface-mount SOIC variant with tape-and-reel packaging.
Replacement Considerations
Direct functional equivalents within the same family include the DG401 and DG403, provided the switch topology matches the circuit requirements. For pin-compatible replacements with different switch configurations, verify logic truth tables and break-before-make timing constraints against the new component's datasheet.
FAQ
What is the guaranteed switching action for the DG405?
The DG405 guarantees a break-before-make switching action for its SPDT configurations, preventing simultaneous connection of both outputs during state transitions.
How does the on-resistance vary with temperature?
The on-resistance is typically 30 Ω at room temperature. It increases to a maximum of 45 Ω across the full operating temperature range (-40 °C to +85 °C) and up to 55 Ω under worst-case conditions.
Is the DG405 latch-up immune?
Yes, the device is built on a proprietary high-voltage silicon-gate process with an epitaxial layer that prevents latch-up, ensuring robust performance.
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