DS1023S-25/T&R

Overview

The DS1023S-25/T&R is an 8-bit programmable timing element manufactured by Analog Devices Inc./Maxim Integrated. It operates on a single 5V supply (4.75V to 5.25V) and features a delay step size of 0.25 ns with a maximum delay range of 63.75 ns relative to the reference output. The device supports both parallel and serial programming modes, allowing flexible configuration as a delay line, pulse width modulator, or free-running oscillator. It is housed in a 16-pin SOIC package and functions within an operating temperature range of 0°C to +70°C.

Feature Summary

• Configurable as a delay line, pulse width modulator, or free-running oscillator
• Supports both parallel and serial programming interfaces
• Includes an on-chip reference delay for accurate phase variation
• Guaranteed monotonicity across all programmed steps

Applications

• Clock phase control applications requiring full 0-360 degree variation
• Pulse width modulation circuits triggered by input waveforms
• Free-running oscillator designs using external feedback connections

Procurement Notes

Verify the specific suffix designation against official documentation to confirm packaging type and environmental compliance. Ensure that the ordering information matches the required voltage and temperature specifications for the target application environment before finalizing procurement.

Selection Notes

Select this component when precise 8-bit programmable delay is required with a 0.25 ns resolution. Consider the available output modes including delayed, inverted, PWM, and reference outputs. Verify that the system interface supports either parallel DC level inputs or serial clock/data shifting for programming the internal register.

Part Context

This part belongs to the DS1023 family of 8-bit programmable timing elements. It shares functional similarities with the DS1020 and DS1021 but includes architectural revisions to allow clock delays exceeding one full period. The 'S' suffix indicates the SOIC package variant, while the '-25' designator specifies the 0.25 ns step size option.

Replacement Considerations

DS1023S-50+T

FAQ

How does the on-chip reference delay improve accuracy?

The reference delay compensates for the inherent 'step zero' delay caused by input and output buffer propagation. Using it removes variations caused by input voltage levels and transition times, ensuring accurate relative timing measurements.

Can the DS1023S-25 delay a clock signal by more than one period?

Yes, the internal architecture allows the output delay time to be considerably longer than the input pulse width, enabling clock signals to be delayed by up to a full period or more.

What is the minimum reliable output pulse width in PWM mode?

In Pulse Width Modulation mode, the minimum output pulse width for reliable operation is approximately 5 ns. Programmed values less than this may result in degraded output voltage levels or no discernible output pulse.