DS90CR485VSX/NOPB

Overview

The DS90CR485VSX/NOPB is a serializer that converts 24 LVCMOS/LVTTL double-edge inputs into 8 Low Voltage Differential Signaling (LVDS) streams. It supports data rates up to 6.384 Gbps with input clocks ranging from 66 MHz to 133 MHz. The device operates on a 2.5V core supply and a 3.3V tolerant I/O supply, housed in a 100-pin TQFP package.

Feature Summary

• Serializes 48 bits of data per clock cycle onto eight differential LVDS channels plus one parallel transmit clock channel.
• Includes pre-emphasis capability to reduce cable loading effects and DC balance mode to minimize inter-symbol interference distortion.
• Features a built-in pseudo-random binary sequence generator for signal quality testing and eye pattern analysis.

Applications

• High throughput point-to-point applications requiring EMI reduction
• Video display interfaces utilizing Channel-Link technology
• Backplane interconnects with controlled differential line impedance

Procurement Notes

Verify the component matches the specific Texas Instruments part number DS90CR485VSX/NOPB. Confirm the suffix indicates the correct tape and reel packaging variant. Ensure the manufacturer documentation aligns with the requested specifications before finalizing acquisition.

Selection Notes

Select this serializer when interfacing wide TTL buses to LVDS links to reduce cabling complexity. Ensure the system design accommodates the required 2.5V and 3.3V power rails. Verify compatibility with downstream receivers such as the DS90CR486 or DS90CR484 for proper deskew initialization.

Part Context

This component belongs to the National Semiconductor DS90CR485 series of Channel-Link serializers. It is designed to work in conjunction with compatible deserializers to form high-speed serial links. The VSX/NOPB designation specifies the industrial temperature range and lead-free compliant packaging.

Replacement Considerations

The DS90CR485 is backward compatible with the DS90CR482 and DS90CR484 receiver families. Direct pin-compatible replacements within the same family should be verified against the official datasheet for electrical parameter alignment.

FAQ

How is the pre-emphasis level configured?

Pre-emphasis strength is set by applying a DC voltage level to the PRE pin using an external pull-up resistor to VCC. The resistor value determines the magnitude of dynamic current during data transitions.

What is the function of the TSEN pin?

The TSEN pin reports the presence of a remote termination resistor. It outputs a low logic state if no termination is detected and a high logic state if a 100 Ω termination is present at the far end of the link.

How does the device handle power-down?

Asserting the PD pin low activates the power-down function, minimizing power dissipation and shutting down the PLL. The transmitter outputs enter a tri-state condition during this mode.