EP2S60F672C4N

Field Programmable Gate Array Overview

The Altera EP2S60F672C4N is a Stratix II Field Programmable Gate Array (FPGA) manufactured on a 1.2-V, 90-nm process. It features 60,440 equivalent logic elements and 3,022 Adaptive Logic Blocks (LABs). The device includes 2,544,192 total RAM bits organized in TriMatrix memory blocks and 36 DSP blocks with 144 multipliers. It supports up to 492 user I/O pins within a 672-pin FineLine BGA package measuring 27x27 mm. Operating voltage ranges from 1.15V to 1.25V, with a commercial temperature range of 0°C to 85°C.

Field Programmable Gate Array Feature Summary

• Stratix II architecture with 60,440 LEs and 2.5 Mbits of TriMatrix memory
• 36 dedicated DSP blocks supporting 18-bit x 18-bit multiplication
• Up to 12 PLLs for clock management and phase shifting
• Support for high-speed interfaces including DDR/DDR2 SDRAM and QDR II SRAM

Field Programmable Gate Array Applications

• High-efficiency image matching systems utilizing parallel MAC arrays
• Real-time correlation coefficient calculation for variable-size images
• Complex digital signal processing and filter implementations

Field Programmable Gate Array Procurement Notes

Verify component authenticity as the EP2S60F672C4N has reached End-of-Life status. Confirm RoHS compliance, noting that earlier speed grades like C3 may lack this certification while C4N typically complies. Validate supply chain sources due to discontinuation and potential availability of refurbished or obsolete stock.

Field Programmable Gate Array Selection Notes

Select the EP2S60F672C4N for designs requiring vertical migration within the 672-pin package alongside EP2S15 and EP2S30 devices. Ensure Quartus II software settings enable migration paths if pin compatibility across densities is required. Verify that the 492 available I/O pins meet interface requirements after accounting for dedicated power and configuration pins.

Field Programmable Gate Array Part Context

This component belongs to the Stratix II family, which introduced Adaptive Logic Modules (ALMs) to maximize resource efficiency. The EP2S60 represents a mid-range density option in the 672-pin package, bridging lower-density EP2S30 and higher-density EP2S90 devices while sharing identical pinouts for specific configurations.

Field Programmable Gate Array Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. As the device is discontinued, consider migrating to newer Intel FPGA families such as Cyclone V or Arria V, though these require significant schematic and software redesign.

Field Programmable Gate Array FAQ

What is the maximum number of DSP blocks in the EP2S60?

The EP2S60 contains 36 DSP blocks, providing a total of 144 18-bit x 18-bit multipliers.

Does the EP2S60 support hot socketing?

Yes, Stratix II devices support hot socketing, allowing I/O pins to remain tri-stated during power-up and preventing drive conflicts before power is applied.

What is the package dimension for the F672 variant?

The 672-pin FineLine BGA package measures 27 mm by 27 mm with a 1.00 mm pitch.