FIN3386MTDX

Overview

The FIN3386MTDX is a low-voltage, 28-bit flat panel display link deserializer manufactured by onsemi. It converts four serial Low Voltage Differential Signaling (LVDS) data streams back into 28-bit or 21-bit Low-Voltage TTL (LVTTL) data. The device supports shift clock frequencies from 20MHz to 85MHz, achieving high throughput up to 2.38Gbps. It operates within a supply voltage range of 3.0V to 3.6V and an operating temperature range of -40°C to +85°C. The component features an internal Phase-Locked Loop (PLL), eliminating the need for external components, and complies with the TIA/EIA-644 specification. It is housed in a 56-lead Thin-Shrink Small-Outline Package (TSSOP).

Feature Summary

• Integrates an internal PLL requiring no external components for clock recovery.
• Supports narrow bus configurations to reduce cable size and cost.
• Provides fail-safe operation and power-down modes to minimize power consumption.
• Compatible with TIA/EIA-644 LVDS specifications.

Applications

• Flat panel display links
• High-speed parallel-to-serial data conversion systems

Procurement Notes

Verify the specific ordering suffix against current manufacturer documentation, as Fairchild part numbers may have been updated following integration into ON Semiconductor. Confirm that the package width matches the required JEDEC MO-153 standard. Ensure environmental compliance requirements align with the RoHS compliant status indicated in official datasheets.

Selection Notes

Select this component when interfacing wide LVTTL buses with LVDS transmission lines to mitigate EMI issues. Ensure the system design accommodates the specified 3.0V to 3.6V supply voltage range. Verify that the application requires the 56-lead TSSOP footprint and operates within the -40°C to +85°C temperature limits defined for this device.

Part Context

This device functions as the receiver counterpart to the FIN3385 serializer. Together, they form a complete link solution designed to solve electromagnetic interference and cable size problems associated with wide, high-speed TTL interfaces. The pair allows for efficient data transmission over differential signaling channels while maintaining compatibility with standard logic levels at the endpoints.

Replacement Considerations

Check for updated part numbers on the ON Semiconductor website due to nomenclature changes from the Fairchild integration. Verify pinout and electrical characteristics against any legacy equivalents to ensure functional compatibility without redesigning the host circuitry.

FAQ

What is the function of the /PwrDn pin?

The /PwrDn pin is an LVTTL level input that puts the outputs into a high-impedance state when asserted LOW, effectively powering down the device.

Does the FIN3386 require external components for its PLL?

No, the FIN3386 includes an internal Phase-Locked Loop (PLL) that does not require external components for operation.

How does the device handle un-driven inputs?

The device incorporates fail-safe circuitry. If the LVDS inputs are shorted or open, the receiver recognizes the signal and responds normally provided the differential input voltage remains within valid ranges.