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The FX604D4-TR1K is a V.23 compatible modem integrated circuit manufactured by CML Microcircuits, designed for the reception or transmission of asynchronous data at 1200 bits/sec and 75 bits/sec. It operates within a supply voltage range of 3.0V to 5.5V and supports an operating temperature from -40°C to +85°C. The device features a 'Zero-Power' mode with typical current consumption of 1μA, alongside standard operating currents of 1.0mA at 3V and 1.7mA at 5V. It utilizes a 3.579545MHz clock rate and includes optional line equalization and data retiming facilities. The component is housed in a 16-pin SOIC (D4) package.
Verify that the specific ordering suffix corresponds to the required tape and reel quantity configuration. Confirm the package type matches the design requirements, as the D4 suffix indicates the 16-pin SOIC variant. Ensure compatibility with the specified 3.579545MHz crystal frequency for proper FSK operation.
Select this component when a CMOS modem compliant with CCITT V.23 and ETSI specifications is required. It is suitable for designs needing low quiescent current and flexible data handling through internal retiming. Consider the 16-pin SOIC footprint during PCB layout planning.
The FX604 series represents a family of low-power CMOS modems. The FX604D4 specifically denotes the 16-pin Small Outline Integrated Circuit (SOIC) package version. This prefix distinguishes it from other package options like the Plastic DIL (P3) variant while maintaining identical silicon functionality.
CMX604D4
When leaving 'Zero-Power' mode, there must be a delay of 20ms before any transmit data is passed to, or receive data is read from, the device to allow bias levels, filters, and the oscillator to stabilize.
The RDYN pin serves as a 'Ready for data transfer' output from the data retiming circuit. It is an open-drain active-low output that can be used as an interrupt request or wake-up input to the associated microcontroller.
The equalizer is controlled by the RXEQ input pin. When RXEQ is low, the group delay is flat; when high, the filter applies specific group delay characteristics to compensate for line distortion.