SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The FX604P3 is a low-power CMOS integrated circuit designed for the reception and transmission of asynchronous data in accordance with CCITT V.23 and ETSI specifications. It supports full-duplex operation at 1200 bits/sec with an optional 75 bits/sec back channel. The device operates from a 3.0V to 5.5V supply, drawing 1.0mA typically at 3V, and features a 'Zero-Power' mode consuming 1μA. It includes an optional line equalizer and data retiming facility for both transmit and receive paths. The component utilizes a 3.579545MHz crystal clock and is housed in a 16-pin Plastic DIL (P3) package.
Verify the specific ordering suffix P3 corresponds to the 16-pin Plastic DIL package configuration required for your design. Confirm that the manufacturing source aligns with CML Microcircuits standards. Ensure compatibility with the 3.579545MHz crystal frequency specified for correct FSK operation. Review the absolute maximum ratings to prevent damage during integration.
Select this component when a V.23 compliant interface is required with minimal external logic overhead. The integrated data retiming feature simplifies microcontroller software by eliminating the need for a dedicated UART. Consider the operating temperature range of -40°C to +85°C for industrial or outdoor environments. Verify that the 16-pin DIP package fits the available PCB footprint constraints.
The FX604 series belongs to the family of V.23 compatible modems produced by CML Microcircuits. The FX604P3 specifically denotes the variant packaged in a 16-pin Plastic Dual In-Line (DIL) format. This distinguishes it from the SOIC version (FX604D4). The product line is designed for robust performance in standard telephone network environments.
Public confirmed substitute part numbers are not available in the provided documentation. Designers should verify pinout and electrical parameter compatibility if considering alternative vendors for V.23 modem ICs.
The 'Zero-Power' mode is activated by setting both M0 and M1 input pins to a high logic level. In this state, power is removed from all internal circuitry.
The RDYN pin is an open-drain active-low output indicating 'Ready for data transfer'. It is used in conjunction with the data retiming function to signal the microcontroller when data bits are available for reading or writing.
Yes, the XTAL/CLOCK pin can accept an external clock signal. If an external clock is used, the external crystal and capacitors (X1, C1, C2) should not be fitted.