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GAL22V10D-25LPI is listed in the Programmable Logic Device Pld range at ChipApex. The manufacturer field lists Lattice Semiconductor Corporation. Its product description is IC CPLD 10MC 25NS 24DIP. Review the specifications below when checking this part for your BOM.
The GAL22V10D-25LPI is a discontinued high-performance E2CMOS PLD from Lattice Semiconductor. It features 22 I/O pins, 10 macrocells, and a maximum propagation delay of 25 ns. The device operates on a 5V supply with typical current consumption of 75 mA for the low-power variant. It utilizes Electrically Erasable floating gate technology, allowing reprogramming and offering 20-year data retention. The component is housed in a 28-pin Plastic DIP package and supports industrial temperature ranges.
This part number is officially discontinued by Lattice Semiconductor as per Product Change Notification PCN#13-10. Verification of availability should focus on surplus or secondary market sources rather than direct manufacturer distribution. Confirm RoHS compliance status and package authenticity when sourcing from non-original distributors.
Select this device only if legacy compatibility with standard 22V10 fuse maps is required. The 'L' suffix indicates Low Power consumption, while 'I' denotes Industrial grade temperature range (-40°C to +85°C). Ensure programming equipment supports the specific GAL22V10 JEDEC map including the 64-bit electronic signature fuses if that feature is utilized.
The GAL22V10 series represents Lattice's high-performance Generic Array Logic devices using E2CMOS technology. This specific model offers a 25 ns speed grade within the low-power industrial variant lineup. It is functionally compatible with bipolar and UVCMOS 22V10 devices but provides significantly lower power consumption and electrical erasability.
No direct public substitute part numbers are confirmed in the provided documentation due to the discontinued status. Designers may need to evaluate modern CPLD families from Lattice or other vendors for functional equivalence, ensuring pinout and logic density compatibility.
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