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GD25B256EFIGY is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 256MBIT SPI/QUAD 16SOP. Review the specifications below when checking this part for your BOM.
The GD25B256EFIGY is a 256M-bit (32M-Byte) Serial NOR Flash memory device manufactured by GigaDevice. It supports Standard, Dual, and Quad SPI interfaces with a maximum clock frequency of 133MHz under a 30pF load. The device operates on a single power supply voltage ranging from 2.7V to 3.6V. It features uniform sector architecture with 4K-Byte sectors and 32/64K-Byte blocks. The SOP-16 package provides hardware reset functionality via the RESET# pin.
Verify the specific suffix FIGY corresponds to the SOP-16 300mil package configuration. Confirm that the required operating voltage range aligns with the 2.7V to 3.6V specification. Ensure design compatibility with the standard SPI interface signals including CS#, SCLK, SI, SO, and RESET#. Check for any specific environmental ratings if operating outside standard commercial temperature ranges.
Select this component when a 256M-bit density is required with Quad SPI support for high throughput. The SOP-16 package is suitable for designs needing a dedicated hardware reset pin. Consider the 133MHz clock speed for latency-sensitive applications. Verify that the 32M-Byte capacity fits the application's code and data storage needs without exceeding available address space.
This part belongs to the GD25B256E series of uniform sector dual and quad serial flash memories. The series offers various package options including WSON8 and TFBGA-24. The GD25B256EFIGY specifically denotes the SOP-16 variant. The series is designed for general-purpose non-volatile storage with high endurance and data retention characteristics.
GD25B256EWIGY
No, the QE bit is permanently set to 1 by default and cannot be changed, ensuring IO2 and IO3 pins are always enabled for Quad SPI operations.
The RESET# pin is a dedicated hardware reset input. Driving it low for at least 1μs resets the flash to standby mode and clears all volatile bits to their power-on defaults.
The device supports both 3-byte and 4-byte address modes. The initial mode upon power-up is determined by the ADP bit in Status Register 3, which can be configured to default to either mode.
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