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GD25LQ128DYIGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 128MBIT SPI/QUAD 8WSON. Review the specifications below when checking this part for your BOM.
The GD25LQ128DYIGR is a 128M-bit (16M x 8) NOR flash memory IC manufactured by GigaDevice. It operates on a single 1.65V to 2.0V power supply and supports Standard, Dual, Quad SPI, and QPI interfaces with a maximum clock frequency of 120 MHz. The device features uniform sector architecture with 4K-byte sectors and 32/64K-byte blocks. It includes hardware and software write protection, a 128-bit unique ID, and security registers. Packaged in an 8-WSON (6x8mm) surface-mount format, it ensures data retention for up to 20 years and withstands at least 100,000 program/erase cycles.
Verify the specific package variant matches the required footprint, as the GD25LQ128D series offers multiple packages including WSON-8 (6x8), WSON-8 (5x6), SOP-8, and VSOP-8. Confirm that the voltage range of 1.65V to 2.0V aligns with the target system's power supply rails. Check for automotive-grade requirements, as this specific part number is not explicitly listed as AEC-Q100 qualified in the provided documentation.
Select this component when a low-voltage (1.8V class) operation is required for the memory subsystem. Ensure the design accommodates the 8-WSON (6x8mm) package dimensions. Consider the 120 MHz speed limit if higher throughput is needed, or opt for the 3V family if voltage compatibility is a constraint. Verify that the system supports the necessary SPI command sets for dual and quad operations.
This device belongs to the GD25LQ128D series of 1.8V Uniform Sector Dual and Quad Serial Flash memories. It is designed for applications demanding high performance and low power consumption within a compact form factor. The series shares architectural similarities with other GigaDevice NOR flash products but is distinct in its specific voltage operating range and package offerings.
GD25LQ128DWIGR (WSON-8 5x6mm package)
The Quad Enable (QE) bit defaults to 0 upon power-up, which disables Quad I/O operations on the WP# and HOLD# pins.
Protection can be achieved via software using the SRP bits, hardware by pulling the WP# pin low, or through power-supply lock-down and one-time programmable settings.
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