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GD25LQ32EEIGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 32MBIT SPI/QUAD 8USON. Review the specifications below when checking this part for your BOM.
The GD25LQ32EEIGR is a 32 Mbit (4M x 8) NOR flash memory IC manufactured by GigaDevice. It operates on a single power supply voltage ranging from 1.65 V to 2.0 V and supports SPI, Dual SPI, Quad SPI, and QPI interfaces with a maximum clock frequency of 133 MHz. The device features uniform sector architecture with 4 KByte sectors and 32/64 KByte blocks. It includes advanced security features such as hardware/software write protection and 128-bit unique identification. The component is housed in an USON-8 package and is designed for surface mount installation.
Verify the specific ordering suffix against the manufacturer's official datasheet to confirm package type and temperature range. Ensure compatibility with the target system's voltage levels, as this part requires a 1.65 V to 2.0 V supply. Confirm that the design accounts for the USON-8 package dimensions and soldering requirements specified in the package information section of the documentation.
Select this component when a low-voltage (1.65 V–2.0 V) NOR flash solution is required for space-constrained designs. The USON-8 package offers a compact footprint suitable for portable applications. Consider the Quad I/O and QPI capabilities if high-speed data retrieval is critical for system performance. Ensure the application environment falls within the specified commercial temperature range of -40°C to +85°C.
This part belongs to the GD25LQ32E series of uniform sector dual and quad serial flash memories. The series is characterized by its support for multiple interface modes and robust data protection mechanisms. The 'EE' suffix typically denotes specific package and temperature variations within the broader GD25LQ32 product family, distinguishing it from other variants like SOP or WSON packages.
GD25LQ32ESIGR
The HOLD function is available only when the Quad Enable (QE) bit is set to 0. If QE is 1, the HOLD function is disabled, and the HOLD# pin acts as a dedicated data I/O pin (IO3).
The Complement Protect (CMP) bit works in conjunction with the Block Protect (BP4-BP0) bits to provide flexibility in defining protected memory areas, allowing for different protection schemes depending on whether the complement is enabled.
No, the Security Register Lock bits (LB3, LB2, LB1) are One Time Programmable (OTP). Once set to 1, the corresponding security registers become permanently read-only and cannot be modified again.
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