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GD25Q20EKIGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 2MBIT SPI/QUAD 8USON. Review the specifications below when checking this part for your BOM.
The GD25Q20EKIGR is a 2 Mbit (256K x 8) NOR flash memory manufactured by GigaDevice. It supports Standard, Dual, and Quad SPI interfaces with a maximum clock frequency of 133 MHz for fast read operations. The device operates on a single power supply voltage ranging from 2.7 V to 3.6 V. It features uniform sector architecture with 4 KByte sectors and 32/64 KByte blocks. Key electrical characteristics include a typical standby current of 11 μA and deep power-down current of 1 μA. The component ensures data integrity through a minimum of 100,000 program/erase cycles and 20-year data retention.
Verify the specific package variant (SOP8 or USON8) required for your design, as the base part number covers multiple physical packages. Confirm the temperature grade matches your operational environment requirements. Ensure compatibility with your system's voltage levels and SPI interface timing constraints before finalizing procurement. Cross-reference the manufacturer's latest datasheet for any updates to command sets or electrical specifications.
Select this component when a 2 Mbit capacity is sufficient for code or data storage needs. It is suitable for applications requiring low power consumption and high reliability. Consider the Quad SPI capability if higher data throughput is necessary compared to standard SPI. Evaluate the available package options against your PCB space constraints and assembly requirements.
This part belongs to the GD25Q20E series of uniform sector serial flash memories. It is designed for general-purpose non-volatile storage applications. The series offers a balance of performance, power efficiency, and robustness. It complements other densities in the GigaDevice portfolio for scalable memory solutions.
GD25Q20ESIGR
The HOLD# pin pauses serial communication without deselecting the chip, while the WP# pin provides hardware-based write protection for the memory array and status register.
When the QE bit is set to 1, the WP# and HOLD# pins function as bidirectional I/O pins (IO2 and IO3) to support Quad SPI operations.
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