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GD25Q64EYIGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 64MBIT SPI/QUAD 8WSON. Review the specifications below when checking this part for your BOM.
The GD25Q64EYIGR is a 64 Mbit (8M x 8) SPI NOR Flash memory component manufactured by GigaDevice. It supports standard, Dual, and Quad SPI interfaces with a maximum clock frequency of 133 MHz. The device operates within a voltage range of 2.7 V to 3.6 V and features uniform sector architecture with 4 KByte sectors and 32/64 KByte blocks. It includes hardware and software write protection, a 128-bit unique ID, and security registers. The part is housed in an 8-lead USON package.
Verify the specific suffix 'YIGR' against the manufacturer's official ordering guide to confirm the exact package type and tape/reel specifications. Ensure compatibility with the required operating voltage range of 2.7V to 3.6V. Confirm that the design supports the necessary SPI interface signals including CS#, SCLK, SI, SO, WP#, and HOLD#. Check for any specific moisture sensitivity level requirements during assembly.
Select this component when a 64 Mbit capacity with uniform sector organization is required. It is suitable for designs needing high-speed read access via Quad SPI mode. Consider the USON package size if board space is limited. Ensure the application can support the 133 MHz clock speed for optimal performance. Verify that the power supply remains stable above the VWI threshold to prevent unintended resets.
The GD25Q64E belongs to the GD25Q64E series of Serial Flash memories from GigaDevice. This series is designed for high-performance applications requiring fast program/erase speeds and low power consumption. The E variant typically denotes specific electrical characteristics and package options within the broader GD25Q64 family, which includes various pin-compatible packages like SOP8 and WSON8.
GD25Q64ESIGR
The QE (Quad Enable) bit allows the device to operate in Quad SPI mode. When set to 1, the WP# and HOLD# pins function as bidirectional I/O pins (IO2 and IO3). If QE is 0, these pins retain their dedicated functions.
The Hold function pauses serial communication without resetting internal logic. It requires CS# to remain low and activates on the falling edge of the HOLD# signal while SCLK is low. Communication resumes when HOLD# goes high while SCLK is low.
The device supports Sector Erase (4 KByte), 32 KByte Block Erase, 64 KByte Block Erase, and Chip Erase. The architecture uses uniform sectors, meaning all sectors are the same size.
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