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GD25Q64EZIGY is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 64MBIT SPI/QUAD 24TFBGA. Review the specifications below when checking this part for your BOM.
The GD25Q64EZIGY is a 64M-bit (8M x 8) NOR flash memory manufactured by GigaDevice. It supports standard, dual, and quad SPI interfaces with a maximum clock frequency of 133 MHz. The device operates on a single power supply ranging from 2.7V to 3.6V. It features uniform sector architecture with 4K-byte sectors and 32/64K-byte blocks. Key specifications include a typical page program time of 0.5ms, block erase times of 150ms or 250ms, and chip erase time of 25s. Data retention is typically 20 years with endurance of at least 100,000 program/erase cycles.
Verify the specific package suffix 'ZIGY' against the manufacturer's official ordering information table to confirm physical dimensions and lead-free status. Ensure compatibility with the required SOP-8 footprint and check for any special handling requirements related to moisture sensitivity level 3.
Select this component when a 64M-bit capacity with uniform sector architecture is required. It is suitable for designs needing high-speed quad SPI access and robust data protection features. Consider the operating voltage range of 2.7V to 3.6V and the industrial temperature range availability if specified in the full datasheet.
This part belongs to the GD25Q64E series of uniform sector dual and quad serial flash memories. The series offers various package options including SOP-8, USON, WSON, and TFBGA. The GD25Q64E family is designed for cost-effective, high-performance non-volatile storage solutions in consumer and industrial electronics.
GD25Q64ESIGY
The Quad Enable (QE) bit allows Quad SPI operation. When set to 1, the WP# and HOLD# pins act as bidirectional I/O pins (IO2 and IO3). When 0, these pins retain their dedicated functions.
The Hold function pauses serial communication without resetting internal logic. It requires CS# to remain low and starts on the falling edge of HOLD# when SCLK is low. It ends on the rising edge of HOLD# when SCLK is low.
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