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GD25WQ128EQIGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 128MBIT SPI/QUAD 8USON. Review the specifications below when checking this part for your BOM.
The GD25WQ128EQIGR is a 128M-bit (16M x 8) Serial NOR Flash memory manufactured by GigaDevice. It supports Standard, Dual, and Quad SPI interfaces with a maximum clock frequency of 104 MHz for fast read operations. The device operates on a single power supply voltage ranging from 1.65 V to 3.6 V. It features uniform sector architecture with 4 K-byte sectors and 32/64 K-byte blocks. Key electrical characteristics include a typical standby current of 14 μA and deep power-down current of 0.1 μA. The memory organization allows for page programming of up to 256 bytes per page.
Verify the specific package variant corresponding to the suffix 'IGR' against the manufacturer's ordering information table. Confirm that the required voltage range and interface modes align with system design constraints. Ensure compatibility with existing SPI controller drivers for Dual and Quad modes. Check for any special order requirements regarding reset pin configurations or security register locks.
Select this component when a 128 Mbit capacity is required with wide voltage support from 1.65 V to 3.6 V. It is suitable for designs needing low power consumption in standby and deep power-down modes. Consider this part for applications requiring uniform sector erase sizes for simplified file system management. Verify that the USON-8 package fits the available PCB real estate constraints.
This device belongs to the GD25WQ128E series of Dual and Quad Serial Flash memories. The series is designed for high-performance code storage with flexible architecture options. It complements other GigaDevice flash products by offering a balance of speed, endurance, and power efficiency for various market segments.
GD25WQ128EWIGR
The function depends on the HOLD/RST bit in Status Register No. 3. When set to 0, it acts as a HOLD# pin to pause serial communications. When set to 1, it acts as a RESET# pin to reset the device internally.
Quad SPI mode is enabled by setting the Quad Enable (QE) bit to 1 in Status Register No. 2. This reconfigures the WP# and HOLD#/RESET# pins as bidirectional I/O pins IO2 and IO3.
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