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GD25WQ64E3IGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 64MBIT SPI/QUAD 14WLCSP. Review the specifications below when checking this part for your BOM.
The GD25WQ64E3IGR is a 64 Mbit (8M x 8) SPI NOR flash memory manufactured by GigaDevice. It supports standard, dual, and quad SPI interfaces with a maximum clock frequency of 104 MHz. The device operates on a single power supply ranging from 1.65 V to 3.6 V. It features uniform sector architecture with 4 KByte sectors and 32/64 KByte blocks. Key electrical parameters include a typical standby current of 12 μA and deep power-down current of 0.1 μA. Endurance is rated for a minimum of 100,000 program/erase cycles with 20-year data retention.
Verify the specific package variant required, as the GD25WQ64E series is available in multiple packages including WLCSP-14, USON-8, SOP-8, and TFBGA-24. Confirm that the ordering suffix matches the desired physical footprint and lead time requirements. Ensure compatibility with the host system's voltage levels and interface support for dual or quad SPI operations if higher speeds are needed.
Select this component when a 64 Mbit capacity with low power consumption and high reliability is required. It is suitable for applications needing uniform sector erase capabilities and robust data protection features. Consider the operating temperature range of -40°C to +85°C for industrial environments. Ensure the design supports the necessary dummy cycle configurations for optimal performance at 104 MHz.
The GD25WQ64E belongs to GigaDevice's GD25WQ series of SPI NOR flash memories. This family is designed for high-performance and low-power applications, offering various package options to suit space-constrained designs. The series emphasizes reliability with AEC-Q100 qualification for automotive-grade variants and functional safety certification.
GD25WQ64ENIGR
When the QE bit is set to 0, the HOLD function is available via the HOLD# pin. When QE is set to 1, the HOLD function is disabled, and the HOLD# pin acts as a dedicated data I/O pin (IO3).
The DC bit selects the number of dummy cycles between the end of the address and the start of read data output. This provides additional latency needed to complete initial read access before data can be returned, especially at higher frequencies like 104 MHz.
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