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GD25WQ64ENEGR is listed in the Memory IC range at ChipApex. The manufacturer field lists GigaDevice Semiconductor (HK) Limited. Its product description is IC FLASH 64MBIT SPI/QUAD 8USON. Review the specifications below when checking this part for your BOM.
The GD25WQ64ENEGR is a 64M-bit (8M x 8) Serial NOR Flash memory manufactured by GigaDevice. It supports Standard, Dual, and Quad SPI interfaces with a maximum clock frequency of 104 MHz for fast read operations under a 30 pF load. The device operates on a single power supply voltage ranging from 1.65 V to 3.6 V. It features a uniform sector architecture with 4 K-byte sectors and 32/64 K-byte blocks. Key electrical characteristics include a typical standby current of 12 μA and a deep power-down current of 0.1 μA. The memory organization allows for page programming of up to 256 bytes.
Verify the specific package variant against the datasheet, as the ENEGR suffix corresponds to the USON-8 (3x4mm) package. Confirm that the required operating voltage range aligns with the 1.65V to 3.6V specification. Ensure compatibility with the host controller's SPI interface modes, particularly if utilizing Quad I/O commands which require setting the QE bit in the status register.
Select this component when a low-voltage operation down to 1.65V is required alongside high-speed Quad SPI access. It is suitable for applications needing robust data protection through hardware WP# pin locking or software block protection. Consider this part for designs requiring a small footprint using the USON-8 package while maintaining industrial-grade endurance and data retention specifications.
The GD25WQ64E series belongs to GigaDevice's Uniform Sector Dual and Quad Serial Flash family. This series is designed for high-performance embedded applications requiring reliable non-volatile storage. The GD25WQ64ENEGR specifically utilizes the USON-8 (3x4mm) package, offering a compact solution for space-constrained designs compared to larger SOP or WSON packages available within the same product line.
GD25WQ64ENIGR
When the QE bit is set to 1, the HOLD# and WP# pins function as bidirectional I/O pins (IO3 and IO2) for Quad SPI operations, disabling the standard Hold and Write Protect functions.
The DC bit configures the number of dummy cycles between the address phase and data output phase during Fast Read commands, ensuring proper timing at higher clock frequencies like 104 MHz.
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