GTL2006PW,118

Translators, Level Shifters Overview

The GTL2006PW,118 is a 13-bit translator designed to interface between 3.3 V LVTTL chip set I/O and Xeon processor GTL–/GTL/GTL+ I/O. It operates as a GTL–/GTL/GTL+ to LVTTL sampling receiver or an LVTTL to GTL–/GTL/GTL+ driver. The device supports 3.0 V to 3.6 V operation with series termination on the LVTTL outputs of 30 Ω. Propagation delay from An to Bn or Bn to An is typically 5.5 ns at CL = 50 pF and VCC = 3.3 V. The component includes ESD protection exceeding 2000 V HBM and latch-up testing exceeding 500 mA.

Translators, Level Shifters Feature Summary

• Translates signals between 3.3 V LVTTL chip sets and Xeon processor GTL–/GTL/GTL+ interfaces
• Provides platform health management capabilities for dual processor applications
• Features integrated ESD protection and robust latch-up resistance

Translators, Level Shifters Applications

• Platform health management in dual processor systems
• Interfacing LVTTL chipsets with Xeon processor I/O
• Monitoring and driving CPU PROCHOT# signals

Translators, Level Shifters Procurement Notes

Verify the specific ordering code GTL2006PW against the required temperature range of –40 °C to +85 °C. Confirm that the TSSOP28 package matches your board layout constraints. Ensure that the 3.0 V to 3.6 V supply voltage requirements align with your system design. Check that LVTTL inputs are not exposed to 5 V levels as they are not 5 V tolerant.

Translators, Level Shifters Selection Notes

Select this component when interfacing 3.3 V LVTTL logic with Xeon processor GTL–/GTL/GTL+ signals. It is suitable for dual processor platforms requiring health management features. Consider the 30 Ω series termination on LVTTL outputs and the non-5 V tolerant nature of the LVTTL I/O. Verify compatibility with the required operating temperature range of –40 °C to +85 °C.

Translators, Level Shifters Part Context

The GTL2006 is part of Philips Semiconductors' (now NXP) product line of level translators. It specifically addresses the need to bridge different voltage domains in high-performance computing environments. The device replaces older translation solutions by integrating multiple channels into a single TSSOP28 package, simplifying board design for dual processor architectures.

Translators, Level Shifters Replacement Considerations

The datasheet indicates that the GTL2006 supersedes data from December 18, 2003. No direct substitute part numbers are provided in the source material.

Translators, Level Shifters FAQ

Are the LVTTL inputs high impedance when the device is unpowered?

Yes, when the device is unpowered, the LVTTL inputs will be in a high-impedance state and will not leak to VDD if pulled high.

Can the GTL2006 operate with VTT of 1.2 V and VREF of 0.6 V?

Yes, you can operate VTT up to 3.6 V and VREF between 0.5 V to 1.8 V at any VTT to adjust noise margins.

What causes the slow transition time for Bn to Bn paths?

The enable time is deliberately slow to prevent glitches or false LOWs on the 7BOn outputs due to potentially slow rise times on open-drain I/Os like 5A and 6A.