HEC4013BT/C5J

$0.09

Description：HEC4013BT - Dual D-type flip-flo
Series：-
Mfr：Nexperia USA Inc.
Package：Bulk

SKU:00a3ea6b921b Category: Flip Flops Brand: Nexperia USA Inc.

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Product introduction

Product Detailed Parameters

Description：HEC4013BT - Dual D-type flip-flo
Series：-
Mfr：Nexperia USA Inc.
Package：Bulk
Function：-
Type：-
Output Type：-
Number of Elements：-
Number of Bits per Element：-
Clock Frequency：-
Max Propagation Delay @ V, Max CL：-
Trigger Type：-
Current - Output High, Low：-
Voltage - Supply：-
Current - Quiescent (Iq)：-
Operating Temperature：-
Mounting Type：-
Supplier Device Package：-
Package / Case：-
Input Capacitance：-
Grade：-
Qualification：-

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HEC4013BT/C5J

Overview

The HEC4013BT/C5J is a dual D-type edge-triggered flip-flop manufactured by Nexperia USA Inc. It belongs to the HEF4000B CMOS logic series and is housed in a 14-pin SOIC package. The device features independent direct set (SD) and direct clear (CD) inputs, along with clock (CP) and data (D) inputs. It operates within a supply voltage range of 3 V to 15 V and supports a maximum clock frequency of 40 MHz. Propagation delay is specified at 60 ns under standard conditions.

Feature Summary

Dual D-type flip-flops with independent asynchronous set and clear functions
Schmitt-trigger clock input for tolerance to slow signal transitions
Fully static operation with low power consumption characteristics
Complementary buffered outputs for optimized system performance

Applications

Industrial control systems requiring reliable data storage
General-purpose digital logic circuits
Shift register configurations
Frequency division and counting applications

Procurement Notes

Verify the specific suffix C5J against official Nexperia documentation to confirm tape and reel specifications or marking codes. Ensure the component meets AEC-Q100 requirements if automotive qualification is necessary. Confirm RoHS compliance status through the manufacturer's latest declaration before integration into production.

Selection Notes

Select this component when dual independent D-latching is required in a single package. It is suitable for designs needing high noise immunity and wide voltage flexibility. Consider the 14-SOIC footprint for surface-mount assembly. Verify that the 60 ns propagation delay meets the timing constraints of the target application circuit.

Part Context

This part is part of the HEF4000B family, which provides standardized symmetrical output characteristics. It complies with JEDEC standard JESD 13-B. The device is designed for robust operation in industrial environments, offering high ESD protection capabilities and stable performance across the specified temperature range.