ICS951412AGLF

Overview

The ICS951412AGLF is a system clock synthesizer designed for ATI RS480-based platforms utilizing AMD K8 processors. It integrates a PLL to generate multiple clock signals from a single 14.318 MHz crystal input. The device provides outputs including three 14.318 MHz reference clocks, one 48 MHz USB clock, one HyperTransport seed, one PCI seed, two pairs of K8 CPU clocks, six pairs of SRC/PCI Express clocks, and two pairs of ATIG clocks. It operates on a 3.135 V to 3.465 V supply within a 56-TSSOP package.

Feature Summary

• Generates specific clock sets for AMD K8 systems, including CPU, HTT, PCI, and PCIe (SRC) frequencies.
• Supports Spread Spectrum modulation for EMI reduction with programmable enable via SMBus or pins.
• Features an SMBus interface for full control, allowing individual output enable/disable and frequency selection.
• Includes CLKREQA# and CLKREQB# pins for dynamic output control of SRC clocks.

Applications

• ATI RS480 chipset systems
• AMD K8 processor-based motherboards
• PCI Express (PCIe) clock generation

Procurement Notes

Verify component authenticity through authorized distributors. Confirm RoHS compliance status as the part may be obsolete. Check for lead-free packaging specifications if required by assembly standards. Ensure the 56-TSSOP footprint matches the PCB design. Validate that the operating temperature range meets system requirements.

Selection Notes

Select this component for legacy ATI RS480 architectures requiring precise AMD K8 clock ratios. Ensure the design supports the required 14.318 MHz external crystal. Verify that the 56-TSSOP package dimensions fit the available board space. Confirm that the SMBus interface is accessible for configuration during system initialization.

Part Context

This component belongs to the ICS9514xx series of system clock chips. It is specifically tailored for desktop and workstation platforms based on the AMD K8 architecture. The device replaces discrete clock generators by integrating multiple PLLs and dividers into a single IC.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Due to the specialized nature of this chip for ATI RS480/K8 systems, direct pin-to-pin replacements may require schematic verification.

FAQ

How is the CPU frequency selected?

CPU frequency is selected using the FS0, FS1, and FS2 pins or via the SMBus interface. The specific frequency depends on the logic levels applied to these pins at power-up or written to the configuration register.

What is the function of the IREF pin?

The IREF pin establishes the reference current for the differential current-mode output pairs (SRC clocks). It requires a fixed precision resistor tied to ground, typically 475 ohms, to set the appropriate output current.

Can the SRC outputs be controlled dynamically?

Yes, the SRC outputs can be enabled or tri-stated using the CLKREQA# and CLKREQB# pins. These pins allow dynamic control over specific SRC clock pairs based on system requirements.