IDTCV122CPVG

Overview

The IDTCV122CPVG is a programmable clock generator from the FlexPC™ series, designed for Intel P4 processors. It features four independent PLLs: one for CPU, one for SRC/PCI, one for SATA, and one for 96MHz/48MHz outputs. The device supports crystal input and provides multiple clock outputs including differential CPU/SRC pairs, PCI, USB 48MHz, and REF. Key specifications include a maximum frequency of 400MHz, a supply voltage range of 3.135V to 3.465V, and cycle-to-cycle jitter under 85ps for CPU and SATA clocks. It operates within a commercial temperature range of 0°C to 70°C.

Feature Summary

• Four high-precision N-programmable PLLs dedicated to CPU, SRC/PCI, SATA, and 96MHz/48MHz functions.
• Supports selectable spread spectrum modulation (down and center) with isolated control per clock group.
• Band-gap referenced IREF output reduces VDD variation impact on differential outputs.
• Configurable via SMBus/I2C with selectable output strength for REF, PCI, and 48MHz signals.

Applications

• Intel advanced P4 processor systems
• SATA controller clocking
• PCI and PCIe reference clock generation

Procurement Notes

This component is marked as not recommended for new designs, with a last-time buy date of December 17, 2010. Verification of current availability and potential obsolescence status is required before procurement planning.

Selection Notes

Select this device for legacy Intel P4 platform designs requiring specific clock ratios and low jitter. Ensure the design accommodates the 56-SSOP package and 3.3V supply constraints. Verify that the commercial temperature range (0°C to 70°C) meets system environmental requirements.

Part Context

Originally manufactured by Integrated Device Technology (IDT), which was acquired by Renesas Electronics Corporation. The IDTCV122C belongs to the FlexPC™ family of programmable clock generators tailored for high-performance computing architectures.

Replacement Considerations

Due to the end-of-life status, direct replacements may be limited. Evaluate newer clock generators from Renesas or other vendors that support similar pinouts and electrical characteristics for retrofits.

FAQ

What is the maximum operating frequency supported by the CPU PLL?

The CPU output buffer is designed to support up to 400MHz processor frequencies.

How is the device configured for frequency selection?

Frequency can be selected via hardware pins (FS_A, FS_B, FS_C) latched at power-up or dynamically programmed through the SMBus/I2C interface using index block read/write protocols.

Does the device support spread spectrum modulation?

Yes, it supports both down-spread and center-spread modulation, with selectable magnitude control for each PLL independently.