LAN91C111-NS

Controllers Overview

The LAN91C111-NS is a single-chip Ethernet controller integrating MAC and PHY layers for 10/100 Mbps networks. It operates on a 3.3V supply with 5V tolerant I/O buffers. The device features an 8 Kbyte internal FIFO buffer, supports burst data transfer, and includes auto-negotiation for duplex and speed selection. It provides host interfaces compatible with ISA, ARM, SH, PowerPC, Coldfire, 680X0, 683XX, and MIPS R3000 processors via an 8, 16, or 32-bit bus. The component utilizes a 128-pin QFP package and functions within a commercial temperature range of 0°C to 70°C.

Controllers Feature Summary

• Integrates IEEE 802.3/802.3u compliant MAC and PHY layers into a single mixed-signal chip.
• Supports flexible host connectivity through asynchronous/synchronous bus interfaces including ISA and various embedded processor architectures.
• Includes internal adaptive equalizer and baseline wander correction eliminating the need for external filters.

Controllers Applications

• Embedded system network adapters
• Industrial automation controllers
• Information appliance networking modules

Controllers Procurement Notes

Verify the specific suffix 'NS' against the manufacturer's current datasheet revision to confirm pinout compatibility and package dimensions. Ensure the design accommodates the 128-pin QFP footprint and thermal requirements for the commercial temperature grade. Cross-reference the ordering information with official Microchip documentation to validate RoHS compliance status.

Controllers Selection Notes

Select this component when a unified MAC-PHY solution is required for embedded applications supporting legacy ISA buses or standard RISC processors. Confirm that the host system can provide the necessary 25 MHz reference clock and that the 3.3V power domain aligns with the system architecture. Evaluate the 8 Kbyte memory limit against expected packet buffering needs.

Controllers Part Context

The LAN91C111 series represents a third-generation Fast Ethernet controller designed by SMSC, now part of Microchip Technology. It serves as a software-compatible successor to the LAN9000 family, offering enhanced integration for embedded networking. The -NS suffix specifically denotes the 128-pin Quad Flat Package (QFP) variant intended for surface-mount assembly in commercial environments.

Controllers Replacement Considerations

LAN91C111I-NU: Industrial temperature grade version in TQFP package.

Controllers FAQ

Does the LAN91C111-NS require external filters for 100Base-TX operation?

No, the device integrates internal output wave shaping circuitry and on-chip filters, eliminating the need for external filters typically required in 100Base-TX applications.

What is the maximum frequency for the local bus clock (LCLK)?

The maximum frequency for the LCLK is 50 MHz in VL Bus mode and limited to 8.33 MHz for EISA slave DMA mode.