LMK1D2102RGTT

Clock Buffers, Drivers Overview

The LMK1D2102RGTT is a low additive jitter LVDS clock buffer manufactured by Texas Instruments. It features dual 1:2 differential buffering, distributing two inputs (IN0, IN1) to four LVDS outputs (OUT0–OUT3). The device supports input frequencies up to 2 GHz and operates on a supply voltage of 1.71 V to 3.465 V. Key electrical parameters include a maximum propagation delay of 575 ps, output skew of 20 ps, and random additive jitter below 60 fs RMS at 156.25 MHz. It accepts universal input levels including LVDS, LVPECL, HCSL, CML, and LVCMOS. The component is housed in a 3 mm × 3 mm 16-pin VQFN package.

Clock Buffers, Drivers Feature Summary

• Dual 1:2 differential LVDS buffer with universal input compatibility (LVDS, LVPECL, HCSL, CML, LVCMOS)
• Low additive jitter (< 60 fs RMS at 156.25 MHz) and very low phase noise floor (-164 dBc/Hz typical)
• Very low propagation delay (< 575 ps max) and output skew (20 ps max)
• Fail-safe input operation with input hysteresis to prevent random oscillation

Clock Buffers, Drivers Applications

• Telecommunications and networking
• Medical imaging
• Test and measurement
• Wireless infrastructure
• Pro audio, video and signage

Clock Buffers, Drivers Procurement Notes

Verify the ordering suffix 'RGT' corresponds to the 16-pin VQFN package configuration. Confirm that the specific revision level matches the design requirements, as datasheets are subject to updates. Ensure the procurement source provides valid traceability for this Texas Instruments component.

Clock Buffers, Drivers Selection Notes

Select the LMK1D2102RGTT when a dual-bank buffer with only two outputs per bank is required, offering a smaller footprint than the 8-output LMK1D2104. Verify that the system requires exactly four LVDS outputs total. Check that the input signal levels match the supported universal inputs and that the 50 Ω transmission line driving capability meets the PCB layout constraints.

Clock Buffers, Drivers Part Context

This component belongs to the LMK1D210x family of ultra-low additive jitter LVDS buffers. The family includes variants such as the LMK1D2104 (dual 1:4), LMK1D2106M (dual 1:6), and LMK1D2108M (dual 1:8). All members share similar electrical characteristics regarding jitter and input compatibility but differ in output count and package size.

Clock Buffers, Drivers Replacement Considerations

LMK1D2104RGTR: Offers eight outputs instead of four in the same package; verify pin compatibility if unused pins are left floating or terminated.

Clock Buffers, Drivers FAQ

How does the EN pin control the output banks?

When the EN pin is open, all outputs are enabled. A logic '0' disables both banks. A logic '1' enables one bank while disabling the other.

Can unused inputs be left floating?

Yes, unused inputs can be left floating due to the device's fail-safe input operation and input hysteresis, which prevents random oscillation.

What is the recommended termination for unused outputs?

TI recommends terminating unused outputs differentially with a 100 Ω resistor for optimum performance, although unterminated outputs are also acceptable.