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The LMKDB1108Z100RKPT is an ultra-low jitter LP-HCSL clock buffer from the LMKDB11xx family, designed for PCIe Gen 1 through Gen 7 applications. It features one differential input and eight differential outputs with a fixed 100Ω output impedance. The device supports both Common Clock (CC) and Independent Reference (IR) architectures and accepts input clocks with or without Spread Spectrum Clocking (SSC). Key electrical specifications include a maximum additive jitter of 31fs RMS (12kHz to 20MHz at 156.25MHz), 13fs for PCIe Gen 4, 5fs for Gen 5, 3fs for Gen 6, and 2.1fs for Gen 7. It operates on 1.8V or 3.3V ±10% power supplies within an ambient temperature range of -40°C to +105°C.
Verify the package designation RKP (VQFN, 40-pin, 5mm × 5mm) matches the design footprint. Confirm the Z suffix indicates 100Ω output impedance and the KPT suffix corresponds to the specific reel quantity and tape configuration required for assembly. Ensure the operating voltage aligns with the 1.8V or 3.3V ±10% specification.
Select this part when eight LVCMOS/LP-HCSL compatible outputs are required for PCIe reference clocks. Choose the Z100 variant specifically for 100Ω termination requirements; use Z85 variants if 85Ω is needed. Consider the FS suffix if fail-safe outputs are necessary, as the standard Z100 variant only provides fail-safe inputs. Verify SMBus address pins (^vSADR0_tri, ^vSADR1_tri) are configured correctly for system integration.
This component belongs to the LMKDB11xx family of ultra-low jitter LP-HCSL buffers. It is compliant with Intel DB2000QL specifications. While pin-compatible devices like the LMKDB1120 exist for higher channel counts, the LMKDB1108 provides a balanced solution for systems requiring exactly eight buffered clock outputs with minimal jitter degradation.
LMKDB1108Z85RKT: Identical functionality but with 85Ω output impedance instead of 100Ω. LMKDB1108FSZ100RKT: Includes fail-safe outputs in addition to the standard fail-safe input feature.