LMKDB1120Z100NPPT

Overview

The LMKDB1120Z100NPPT is a high-performance, ultra-low jitter LP-HCSL clock buffer from Texas Instruments. It provides one differential input and twenty differential outputs with a fixed 100Ω output impedance. The device supports PCIe Gen 1 through Gen 7 architectures, including Common Clock (CC) and Independent Reference (IR) configurations, and handles input clocks with or without Spread Spectrum Clocking (SSC). It operates on dual power supplies: 1.8V for analog circuits and 1.8V/3.3V ±10% for outputs. Key features include extremely low additive jitter (max 3fs for PCIe Gen 6), fail-safe inputs, individual output enable control, and SMBus interface capabilities.

Feature Summary

• Ultra-low additive jitter performance: max 31fs RMS (12kHz–20MHz at 156.25MHz), 13fs for PCIe Gen 4, 5fs for Gen 5, 3fs for Gen 6, and 2.1fs for Gen 7.
• Supports PCIe Gen 1 to Gen 7 standards with flexible input clock handling, including SSC compatibility.
• Provides 20 LP-HCSL differential outputs with 100Ω impedance; all inputs are fail-safe.
• Includes SMBus interface for configuration, individual active-low output enables, and Loss of Signal (LOS) detection.

Applications

• High Performance Computing systems
• Server Motherboards
• NIC/SmartNIC designs
• Hardware Accelerators

Procurement Notes

Verify the package type NPP (TLGA, 80 pins, 6mm × 6mm) matches the target PCB footprint. Confirm that the Z suffix indicates the 100Ω output impedance variant, distinct from the Z85 version. Ensure the NPPT suffix corresponds to the required tape and reel quantity for manufacturing integration. Check for RoHS compliance status in the latest datasheet revision.

Selection Notes

Select this component when twenty buffered LP-HCSL outputs are required for PCIe Gen 6 or Gen 7 applications. Choose the Z100 variant specifically if the downstream PHY requires 100Ω termination rather than 85Ω. Consider the LMKDB1120FS variant if fail-safe outputs are necessary alongside the fail-safe inputs. Verify power supply constraints, as using 1.8V for VDDCLK saves approximately 250mW compared to 3.3V operation.

Part Context

This part belongs to the LMKDB11xx family of ultra-low jitter LP-HCSL clock buffers. It is pin-compatible with Intel’s DB2000QL specification, facilitating direct replacement in existing reference designs. The family includes variants with different output counts (LMKDB1112, LMKDB1108) and impedance options (85Ω vs 100Ω). The LMKDB1120 serves as the highest-output buffer in the standard series, supporting up to 20 lanes.

Replacement Considerations

The LMKDB1120Z85NPPT is a direct pin-compatible alternative offering 85Ω output impedance instead of 100Ω. For designs requiring fail-safe outputs, the LMKDB1120FSZ100NPPT provides identical functionality with added output fail-safety. Ensure any substitute maintains support for the specific PCIe generation and jitter requirements of the application.