SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The LS7195S02 is a three-terminal digital potentiometer featuring an incremental encoder interface and SPI communication. It provides 64-position wiper control with non-quadrature up/down clock inputs (A and B) that are not debounced, supporting fast electronic clock sources. The device operates on a 3V to 5V supply and includes an internal 6-bit up/down counter ranging from 0 to 63. It is available in SOIC-8 packages with a 20K resistor value.
Verify the ordering suffix 'S' corresponds to the SOIC-8 package and '02' indicates the 20K resistance value as per the LS71XX-PP-RR designation format. Confirm availability of the specific package variant through official LSI/CSI channels.
Select the LS7195 variant specifically when non-quadrature up/down clock signals are required without hardware debouncing. Ensure the application utilizes electronic clock sources rather than mechanical encoders, as this model lacks the debounce circuitry found in the LS7190/91 series.
The LS7195 belongs to the LS719x family of digital potentiometers. It shares the core 64-tap architecture and SPI interface with models like LS7190 and LS7191 but differs in its input handling configuration, specifically targeting non-quadrature, non-debounced applications.
LS7191S02: Provides similar functionality but includes input debouncing suitable for mechanical encoders.
The internal 6-bit counter freezes at the maximum value (63) or minimum value (0) and does not roll over until the count direction is reversed.
The CAP pin connects an external capacitor to set the debounce oscillator frequency. Although the LS7195 inputs are non-debounced by default, this pin allows for configurable delay settings if needed.
Upon power-up, the wiper terminal Tw is preset to N = 32, which corresponds to the mid-point of the potentiometer.