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The LTC1068CN#PBF is a clock-tunable, quad second-order filter building block from Analog Devices Inc. It integrates four matched, low-noise switched-capacitor filter sections within a 24-lead PDIP package. The device operates with a nominal clock-to-center frequency ratio of 100:1. It supports supply voltages ranging from 3.14V to ±5.5V and functions across an operating temperature range of 0°C to 70°C. Key electrical parameters include a typical power supply current of 8mA at ±5V, a gain-bandwidth product of 6MHz, and a slew rate of 10V/µs.
Verify the specific ordering suffix CN#PBF against the manufacturer's official documentation to confirm the 24-lead PDIP package and commercial temperature range specifications. Ensure compatibility with existing PCB footprints for this package type. Confirm that the required clock-to-center frequency ratio aligns with the standard 100:1 configuration provided by this part variant.
Select this component when a 24-lead PDIP package is required for the LTC1068 family. This variant provides a nominal 100:1 clock-to-center frequency ratio. Consider alternative suffixes if a wider industrial temperature range or a surface mount SSOP package is needed. Verify that the application requires the specific frequency tuning characteristics associated with the 100:1 ratio rather than the 25:1, 50:1, or 200:1 variants.
This component belongs to the LTC1068 series of clock-tunable filter building blocks. The series includes variants with different fixed clock-to-center frequency ratios, specifically 25:1, 50:1, and 200:1. These devices are designed to be used with FilterCAD software for rapid filter design implementation. The CN#PBF designation specifically identifies the commercial grade version housed in a plastic DIP package.
Direct replacements within the same family include LTC1068CG#PBF for SSOP packaging or LTC1068IN#PBF for industrial temperature ranges. Substituting with other LTC1068 variants requires verifying that the clock-to-center frequency ratio matches the original circuit design requirements.