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LTC1604ACG#PBF is listed in the Analog To Digital Converters (ADC) range at ChipApex. The manufacturer field lists Analog Devices Inc.. Its product description is IC ADC 16BIT SAR 36SSOP. Review the specifications below when checking this part for your BOM.
The LTC1604ACG#PBF is a high-speed, 16-bit sampling analog-to-digital converter (ADC) manufactured by Analog Devices Inc. It operates at a maximum sampling rate of 333ksps with a typical power dissipation of 220mW from ±5V supplies. The device features a differential input sample-and-hold circuit with a full-scale input range of ±2.5V and a bandwidth of 5MHz. Key performance metrics include a Signal-to-(Noise + Distortion) ratio of 90dB and Total Harmonic Distortion of –100dB at 333ksps. It integrates an internal reference and offers two digitally selectable shutdown modes for power savings.
Verify the specific grade suffix 'ACG' against the manufacturer's current ordering guide to confirm availability and exact electrical tolerances. Ensure the package type matches the 36-lead plastic SSOP specification. Confirm RoHS compliance status for the specific batch prior to procurement.
Select this component for applications requiring high dynamic range at moderate speeds. The ±2.5V bipolar input range suits direct coupling with op amps. Consider the 333ksps throughput limit when designing system timing. Verify that the required supply voltage aligns with the ±5V specification for optimal performance.
This part belongs to the LTC1604 family of 16-bit sampling ADCs. The 'A' designation typically indicates enhanced accuracy specifications compared to standard grades. The 'CG' suffix denotes the commercial temperature range and SSOP package. It serves as a complete solution with integrated clock, reference, and sample-and-hold circuits.
Check for pin-compatible alternatives within the Analog Devices portfolio if lead times are critical. Ensure any substitute maintains the 16-bit resolution and 333ksps sampling rate. Verify that the replacement supports the same ±5V supply requirements and differential input architecture.
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