LTC6955IUKG-1#PBF

Clock Generators, PLLs, Frequency Synthesizers Overview

The LTC6955IUKG-1#PBF is an ultralow jitter, 7.5GHz fanout buffer family member featuring eleven CML outputs in a 52-lead QFN package. It includes one divide-by-2 output (OUT10) and ten buffered outputs. Key electrical parameters include a supply voltage range of 3.15V to 3.45V, additive RMS jitter of approximately 45fs (ADC SNR method), and less than 5fs RMS (12kHz to 20MHz integration bandwidth). The device operates within a junction temperature range of –40°C to 125°C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Ultralow Jitter: Additive output jitter is ~45fs RMS (ADC SNR Method) and <5fs RMS (12kHz to 20MHz BW at 7.5GHz).
• Flexible Output Configuration: Eleven CML outputs with parallel control allowing 3 to 11 active outputs; OUT10 provides a ÷2 frequency divider.
• High Frequency Operation: Supports input and output frequencies up to 7.5GHz with low skew characteristics.
• Integrated Control Features: Includes FILT pin for noise filtering optimization and TEMP pin for die temperature monitoring.

Clock Generators, PLLs, Frequency Synthesizers Applications

• High Performance Data Converter Clocking
• JESD204B Subclass 1 SYSREF Signal Generation
• SONET, Fibre Channel, and GigE Clock Distribution
• Wireless and Wired Communications Systems

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix #PBF indicates lead-free tube packaging. Confirm the -1 suffix denotes the integrated divide-by-2 output on OUT10. Ensure the UKG package dimensions match the PCB footprint requirements. Check for any product change notifications regarding the 52-lead QFN assembly.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when a dedicated divide-by-2 clock output is required alongside multiple buffered clocks. Compare against the standard LTC6955 if all outputs need to be undivided buffers. Consider the power consumption differences between active output configurations defined by the SELx pins. Verify input signal slew rates to determine if the internal FILT circuitry should be enabled.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the LTC6955 family of ultralow jitter fanout buffers. The -1 variant specifically replaces one buffer output with a frequency divider, designed to pair with devices like the LTC6952 or LTC6953 for JESD204B synchronization. It shares the same 52-lead QFN package and core architecture as the standard LTC6955.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. The standard LTC6955IUKG#PBF serves as a functional alternative if the divide-by-2 feature is not required.