LTC6955IUKG#PBF

Clock Generators, PLLs, Frequency Synthesizers Overview

The LTC6955IUKG#PBF is an ultralow jitter, 7.5GHz fanout clock buffer family member featuring eleven CML outputs. It operates on a 3.15V to 3.45V supply with typical output currents of 420mA when all outputs are active. The device provides additive output jitter of approximately 45fs RMS (ADC SNR method) and less than 5fs RMS within a 12kHz to 20MHz integration bandwidth at 7.5GHz. It includes a four-pin parallel control port for configuring between three and eleven active outputs, supporting polarity inversion for specific channels.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Ultralow Jitter: ~45fs RMS additive jitter (ADC SNR method); <5fs RMS (12kHz-20MHz BW)
• High Frequency: Supports differential CML outputs from DC to 7.5GHz
• Parallel Control: Configurable 3-to-11 outputs via SEL pins; supports output polarity inversion
• Low Skew: Typical skew of ±25ps across multiple parts

Clock Generators, PLLs, Frequency Synthesizers Applications

• High performance data converter clocking
• SONET, Fibre Channel, GigE clock distribution
• Low skew and jitter clock and data fanout
• Wireless and wired communications systems

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the package type is the 52-lead (7mm × 8mm) plastic QFN. Confirm the operating temperature range is –40°C to 125°C. Ensure power supply decoupling capacitors (0.01µF for VOUT+, 0.1µF for VD+) are placed as close to the pins as possible to maintain low ground inductance.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select the standard LTC6955 for eleven identical buffered outputs. Choose the LTC6955-1 variant if a divide-by-2 output is required for generating JESD204B subclass 1 SYSREF signals. Ensure input slew rates exceed 100V/µs or enable the FILT pin for lower slew rate inputs to optimize phase noise.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the LTC6955 family of high-performance clock buffers. It is designed to distribute low-noise clock signals to multiple destinations while maintaining signal integrity. The exposed pad (Pin 53) must be soldered directly to the PCB ground plane for thermal management and electrical grounding.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.