M2020-13-622.0800

Clock Generators, PLLs, Frequency Synthesizers Overview

The M2020-13-622.0800 is a VCSO-based clock jitter attenuator PLL designed for optical network systems supporting 2.5 to 10 Gb/s data rates. It integrates a SAW delay line to achieve low phase jitter, typically less than 0.5 ps rms (12 kHz to 20 MHz). The device operates on a single 3.3V supply and provides differential LVPECL outputs with frequencies ranging from 15 to 700 MHz. Input references support differential LVDS/LVPECL or single-ended LVCMOS/LVTTL signals. Pin-selectable dividers allow configuration of multiplication ratios and output scaling.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrated SAW delay line providing typical output jitter of < 0.5 ps rms
• Dual reference inputs accepting differential LVDS/LVPECL or single-ended LVCMOS/LVTTL
• Pin-selectable M, R, and P dividers for flexible frequency translation
• Narrow Bandwidth (NBW) control pin for adjustable loop bandwidth

Clock Generators, PLLs, Frequency Synthesizers Applications

• Transmit reference clock generation for optical networks
• Jitter attenuation for stratum reference clocks
• Loop timing mode for recovered clock synchronization

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's documentation to confirm temperature grade and optional features such as Hitless Switching or Phase Build-out. Confirm that the required VCSO center frequency matches the fixed internal specification for this part number variant.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when low intrinsic jitter is critical for SONET/SDH applications. Ensure the external loop filter components are sized according to the selected divider settings and NBW configuration. Verify that the input reference frequency allows the PLL to lock within the VCSO tuning range of ±120 ppm.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This model belongs to the M2020/21 series manufactured by Integrated Circuit Systems, Inc., which was acquired by Renesas Electronics Corporation. The device utilizes a proprietary SAW delay line technology to replace traditional crystal oscillators in high-frequency networking equipment.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided source material.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How is the Narrow Bandwidth (NBW) controlled?

The NBW pin adjusts the internal loop resistor (RIN). Logic 1 sets RIN to 2100 kΩ for narrow bandwidth, while Logic 0 sets it to 100 kΩ for wide bandwidth.

What is the function of the LOL pin?

The Loss of Lock (LOL) pin indicates PLL status. It outputs logic 1 if the phase error exceeds 4 ns and returns to logic 0 when the error drops below 2 ns.

Can the device accept single-ended input signals?

Yes, single-ended LVCMOS or LVTTL signals can be applied to the non-inverting reference input pins (DIF_REF0 or DIF_REF1), while the inverting pins remain unconnected.