MAX3671ETN2T

Clock Generators, PLLs, Frequency Synthesizers Overview

The MAX3671ETN2T is a low-jitter frequency synthesizer designed for Gigabit Ethernet applications. It accepts two differential LVPECL reference clock inputs and generates nine phase-aligned LVPECL outputs. The device integrates a PLL with a 2.5GHz VCO, offering 0.3ps RMS integrated jitter (12kHz to 20MHz) and a 40kHz jitter transfer bandwidth. Operating from a single +3.3V supply, it typically consumes 400mW. Key features include selectable input references, external feedback for zero-delay buffer configuration, and clock failure indicators. It is housed in an 8mm x 8mm, 56-pin TQFN package with an exposed pad.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual LVPECL Reference Inputs: Supports selectable REFCLK0 or REFCLK1 via SEL_CLK pin.
• Nine Phase-Aligned Outputs: Generates frequencies of 62.5MHz, 125MHz, 156.25MHz, 250MHz, or 312.5MHz across two groups (A and B).
• Low-Jitter Performance: Achieves 0.3ps RMS integrated phase jitter (12kHz–20MHz) with best-in-class power-supply noise rejection.
• Zero-Delay Buffer Capability: External feedback path selectable via FB_SEL pin for phase synchronization.

Clock Generators, PLLs, Frequency Synthesizers Applications

• Gigabit Ethernet Routers and Switches
• Frequency Translation
• Jitter Cleanup
• Clock Distribution

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific suffix 'ETN2T' against official Microchip/Maxim documentation to confirm tape-and-reel packaging and exact temperature range (-40°C to +85°C). Ensure the source document explicitly links this suffix to the standard MAX3671ETN+ lead-free/RoHS-compliant variant. Confirm availability status as distribution data may vary.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select the MAX3671ETN2T when dual reference clock redundancy and ultra-low jitter (<1ps RMS) are required for Gigabit Ethernet PHYs. Configure output frequencies using four-level control pins (DM, DA, DB). Ensure proper termination of LVPECL outputs to VTT = VCC - 2V. Connect the exposed pad to ground for thermal and electrical performance.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The MAX3671 is part of Maxim Integrated's (now Microchip) low-jitter clock generator family. It is functionally similar to the MAX3697 but optimized for different frequency ranges and interface types. The ETN2T designation indicates the 56-pin TQFN package variant intended for surface-mount assembly.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided datasheet. Verify compatibility with existing designs if replacing with other low-jitter synthesizers, noting differences in input/output voltage levels (LVPECL vs LVDS/LVCMOS) and package footprints.