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MAX9600EUP is listed in the Comparators range at ChipApex. The manufacturer field lists Analog Devices Inc./Maxim Integrated. Its product description is IC COMPARATOR 2 W/LATCH 20TSSOP. Review the specifications below when checking this part for your BOM.
The MAX9600EUP is a dual-channel ultra-high-speed comparator housed in a 20-pin TSSOP package. It features differential ECL outputs and operates from supply voltages of VCC = +5V and VEE = -5.2V, or shifted levels of +6V/-4.2V. The device provides a typical propagation delay of 500ps with a maximum skew of 10ps and dispersion under 30ps. It supports tracking frequencies up to 4Gbps and includes latch-enable and adjustable hysteresis control inputs.
Verify the specific ordering suffix 'EUP' corresponds to the 20-pin TSSOP package variant with dual ECL outputs. Confirm that the application requires ECL logic compatibility rather than PECL. Ensure power supplies match the specified +5V and -5.2V requirements for optimal performance parameters.
Select this component when differential ECL signaling is required alongside precise timing control. The inclusion of latch-enable and hysteresis distinguishes it from standard comparators. Consider the MAX9601 if PECL outputs are preferred instead of ECL, or the MAX9602 for quad-channel density without latch functions.
This part belongs to the MAX9600/MAX9601/MAX9602 family of ultra-high-speed comparators designed by Analog Devices / Maxim Integrated. These devices utilize a bipolar process and are engineered for applications demanding minimal propagation delay and dispersion. The MAX9600 specifically serves as the dual-channel ECL variant within this series.
Public confirmed substitute part numbers: MAX9601EUP (PECL output variant), MAX9602EUG (Quad PECL variant).
Hysteresis is current-controlled and set by placing a resistor between the HYS_ pin and GND. Values ranging from 10kΩ to 35kΩ provide adjustable hysteresis levels.
The LE_ pins control the latch-enable function. Driving them differentially high places the comparator in latch mode, freezing the output state based on the input at the transition time.
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