MAXQ1065GTC+T

Overview

The MAXQ1065GTC+T is a DeepCover security coprocessor providing turnkey cryptographic functions for embedded systems. It supports root-of-trust, mutual authentication, secure boot, and TLS/DTLS 1.2 communications. The device integrates an ECC compute engine (NIST P-256), SHA-2, AES (128/192/256-bit), and a True Random Number Generator compliant with NIST SP800-90A/B/C standards. It features 8KB of secure user flash storage protected by ChipDNA PUF technology. Electrical specifications include a supply voltage range of 1.62V to 3.63V, active current up to 3mA, and standby current of 100nA typ. Interfaces include SPI up to 10MHz and I2C up to 1Mbps.

Feature Summary

• Integrated ECC, SHA-2, and AES engines supporting TLS/DTLS 1.2 handshake and record layer operations.
• 8KB secure nonvolatile memory with user-defined access control and life cycle management.
• ChipDNA PUF technology for encrypted key storage and unique factory-programmed ID.
• Configurable tamper detection input and reset output pin for system-level intrusion protection.

Applications

• Industrial IoT and SCADA network nodes
• Medical equipment and wearable devices
• Smart metering and building automation gateways

Procurement Notes

Verify the specific suffix 'T' indicates tape-and-reel packaging when sourcing components. Confirm RoHS compliance status through official manufacturer documentation or authorized distributors. Ensure the ordering part number matches the required interface configuration, as the MAXQ1065 family includes distinct variants for SPI and I2C communication protocols.

Selection Notes

Select this component for applications requiring hardware-based root-of-trust and low-power operation in battery-constrained environments. The 12-pin TDFN package suits space-constrained designs. Verify that the host microcontroller can support the required SPI or I2C interface speeds. Consider the SDK availability for Mbed OS, Linux, or bare-metal integration during the design phase.

Part Context

The MAXQ1065 belongs to the Analog Devices DeepCover security solution family. It serves as a dedicated cryptographic controller designed to offload security processing from the main host processor. The GTC+ designation identifies the specific package type and commercial temperature grade within the broader MAXQ1065 product line.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult Analog Devices for current equivalent recommendations based on specific interface and performance requirements.

FAQ

What cryptographic curves does the MAXQ1065 support?

The device supports the NIST P-256 (secp256r1) elliptic curve for ECDSA signature generation/verification and ECDHE key exchange.

How is the secure storage protected against physical attacks?

Secure storage uses ChipDNA PUF technology to encrypt keys. It also includes an active die shield and configurable tamper inputs that can trigger zeroization of secret keys upon intrusion detection.

Does the MAXQ1065 support TLS 1.2?

Yes, it provides complete TLS/DTLS 1.2 support, including client-side key negotiation (PSK, ECDH, ECDHE), certificate verification, and record layer encryption using AES-GCM or CCM modes.