MC100ES6139DT

Clock Generators, PLLs, Frequency Synthesizers Overview

The MC100ES6139DT is a low skew clock generation chip from the 100E series, manufactured by Motorola (now NXP USA Inc.). It provides ÷2/4 and ÷4/5/6 division ratios with internal dividers synchronous to each other for precise output edge alignment. The device supports differential or single-ended ECL, LVPECL, HSTL, and LVDS inputs. Operating in PECL mode requires VCC between 3.135 V and 3.8 V with VEE at 0 V; ECL mode uses VCC at 0 V with VEE between –3.135 V and –3.8 V. Maximum frequency exceeds 1.0 GHz typical, with output-to-output skew of 50 ps. It features synchronous enable/disable, master reset, and an open input default state.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Maximum Frequency >1.0 GHz Typical
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable and Master Reset
• LVDS and HSTL Input Compatible

Clock Generators, PLLs, Frequency Synthesizers Applications

• Low skew clock generation applications
• Systems requiring multiple synchronized ES6139 chips
• Single-device systems utilizing ÷2/4 and ÷4/5/6 outputs

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify package type DT suffix corresponds to TSSOP-20. Confirm RoHS compliance status as original datasheet indicates non-compliance. Check current manufacturer availability through NXP channels. Validate operating temperature range requirements against -40°C to +85°C specification. Ensure power supply connections for all VCC and VEE pins are externally connected.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select based on required division ratios: DIVSELa controls ÷2/4 outputs while DIVSELb0 and DIVSELb1 control ÷4/5/6 outputs. Use MR pin for synchronization when multiple chips are employed. Connect VBB output to CLK input via 0.01 µF capacitor for single-ended input configurations. Ensure differential input voltage swing remains within 200 mV to 1200 mV range.

Clock Generators, PLLs, Frequency Synthesizers Part Context

Part of the 100ES Series containing temperature compensation. Originally released by Motorola Semiconductor in June 2004. Later transferred to Freescale Semiconductor. Current branding under NXP USA Inc. The DT suffix specifically denotes the 20-lead TSSOP package (Case 948E-02).

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

MC100ES6139DTR2 offers identical functionality in TSSOP-20 with tape-and-reel packaging. MC100ES6139DW provides the same electrical characteristics in SOIC-20 package.