MC100ES6535EJ

Clock Buffers, Drivers Overview

The MC100ES6535EJ is a discontinued 3.3V LVCMOS-to-LVPECL 1:4 fanout buffer manufactured by Integrated Device Technology (IDT). It translates selectable LVCMOS or LVTTL input levels to four differential LVPECL outputs, supporting a maximum frequency of 1 GHz. The device features an internally synchronized clock enable to prevent runt pulses and operates within a supply range of 3.135 V to 3.8 V. It is housed in a 20-lead Pb-free TSSOP package with an operating temperature range of –40°C to +85°C.

Clock Buffers, Drivers Feature Summary

• Translates LVCMOS/LVTTL inputs to four differential LVPECL outputs
• Maximum output frequency of 1 GHz
• Low skew characteristics: 30 ps max output skew and 190 ps part-to-part skew
• Internally synchronized clock enable eliminates runt pulses

Clock Buffers, Drivers Applications

• High-performance clock distribution systems
• LVCMOS/LVTTL to LVPECL level translation
• Buffering single-ended clock signals for differential loads

Clock Buffers, Drivers Procurement Notes

This component is officially discontinued with a Last Time Buy expiration date of November 18, 2013. Verification of current availability requires checking authorized distributors for remaining stock or obsolete inventory. No new production units are available from the manufacturer.

Clock Buffers, Drivers Selection Notes

Designers requiring this functionality should consider the recommended replacement part ICS8535I-01. Ensure that the target system supports the 3.3V LVPECL output voltage levels and can accommodate the 20-lead TSSOP footprint if retaining the original form factor.

Clock Buffers, Drivers Part Context

The MC100ES6535 series belongs to IDT's low-skew fanout buffer family designed for high-speed clock distribution. The 'EJ' suffix specifically denotes the lead-free version of the 20-lead TSSOP package, distinguishing it from the standard tin-lead 'DT' variant.

Clock Buffers, Drivers Replacement Considerations

The datasheet explicitly recommends the ICS8535I-01 as the replacement part for the MC100ES6535 series.

Clock Buffers, Drivers FAQ

What is the function of the CLK_EN pin?

The CLK_EN pin synchronizes the clock enable signal internally to eliminate runt pulses on the outputs during asynchronous assertion or deassertion.

How is the input source selected?

Input selection is controlled by the CLK_SEL pin; when HIGH, CLK1 is selected, and when LOW, CLK0 is selected.

What are the absolute maximum ratings for power supply voltage difference?

The absolute maximum rating for the voltage difference between VCC and VEE is 3.9 V.