MC10E196FNR2

Overview

The MC10E196FNR2 is a programmable delay chip (PDC) designed for accurate differential ECL input edge placement. It features a chain of gates and a linear ramp delay adjustment, providing a worst-case delay range of 2.0 ns with approximately 20 ps per step resolution. The device includes an FTUNE analog input to further reduce the minimum LSB resolution. It operates in PECL mode with VCC from 4.2 V to 5.7 V (VEE = 0 V) or NECL mode with VEE from -4.2 V to -5.7 V (VCC = 0 V). The component has a bandwidth greater than 1.0 GHz and contains on-chip cascade circuitry for extended programmable ranges.

Feature Summary

• Features a linear ramp delay adjustment via the FTUNE pin to enhance digital resolution capabilities beyond standard 20 ps steps.
• Includes internal cascade logic allowing multiple devices to be chained without external gating, requiring only one additional address line per added unit.
• Provides an internally generated reference voltage output (VBB) available for use as a switching reference or for rebiasing AC coupled inputs.

Applications

• Very accurate differential ECL input edge placement applications
• Clock distribution systems requiring precise timing adjustments
• High-speed data acquisition systems needing fine delay control

Procurement Notes

Verify the specific ordering suffix to confirm package type and shipping quantity. The FNR2 suffix indicates a PLCC-28 package supplied in tape and reel format containing 500 units. Confirm RoHS compliance status if required by the design specifications, noting that Pb-Free variants carry an additional G suffix.

Selection Notes

Select this component when precise programmable delay is required for high-speed ECL signals. Ensure the design supports either PECL or NECL power supply configurations. Consider using the FTUNE pin with an external DAC if sub-20 ps resolution is necessary. Verify that the system can accommodate the required thermal management for the PLCC-28 package.

Part Context

This part belongs to the MC10E/100E196 series of programmable delay chips manufactured by onsemi. It is functionally similar to the MC10E195 but adds the FTUNE analog input for finer resolution. The 100 Series variant includes temperature compensation, whereas the 10 Series does not. Both share the same pinout and core functionality.

Replacement Considerations

The MC10E195 serves as a related model within the same family but lacks the FTUNE analog input feature. When replacing the MC10E196FNR2 with the MC10E195, verify that the application does not require the enhanced resolution provided by the linear ramp delay adjustment.

FAQ

How does the FTUNE pin improve delay resolution?

The FTUNE pin accepts an analog voltage that applies a linear ramp to the internal delay circuitry. This allows for delay adjustments finer than the 20 ps digital resolution provided by the address inputs, effectively reducing the minimum LSB step size.

What is the purpose of the VBB pin?

The VBB pin provides an internally generated reference voltage. It can be used as a switching reference voltage for single-ended input conditions by connecting the unused differential input to it, or to rebias AC coupled inputs.

How are multiple MC10E196 devices cascaded?

Multiple devices are cascaded using the D7 input and the CASCADE outputs. Asserting D7 on the first chip signals the need for additional delay range, which controls the SET MIN pin of the subsequent chip. This allows chaining without external gating, adding only one address line per device.