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MC10EL05DG is listed in the Gates And Inverters - Multi-Function, Configurable range at ChipApex. The manufacturer field lists onsemi. Its product description is IC GATE AND/NAND ECL 2INP 8SOIC. Review the specifications below when checking this part for your BOM.
The MC10EL05DG is a single 2-input differential AND/NAND gate from the onsemi ECL logic family, housed in an SOIC-8 surface-mount package. It operates within a PECL voltage range of 4.2 V to 5.7 V (with VEE at 0 V) or an NECL range with VCC at 0 V and VEE between -4.2 V and -5.7 V. The device features a typical propagation delay of 275 ps at 25°C, with maximum delays reaching 440 ps at -40°C and 390 ps at 85°C under specified conditions. Power supply current typically draws 22 mA across the operating temperature range of -40°C to +85°C.
Verify the specific ordering suffix 'DG' corresponds to the SOIC-8 tube packaging configuration. Confirm RoHS compliance status and lead times directly with authorized distributors, as availability may vary. Ensure design specifications align with the documented thermal resistance and moisture sensitivity levels for the selected package style.
Select this component when ultimate AC performance is required compared to legacy equivalents like the E404. Consider the MC100EL05DG variant if temperature compensation is necessary for stable operation across varying thermal environments. Verify power supply configurations match either PECL or NECL requirements before integration.
This device belongs to the MC10EL/100EL series of ECL logic gates manufactured by onsemi. It serves as a high-performance replacement for older discrete logic devices, offering significantly faster propagation delays and output transition times. The series supports both standard and temperature-compensated variants within the same functional architecture.
Functionally equivalent to the E404 device but offers superior speed characteristics. Designers should verify pinout compatibility and electrical parameter margins when substituting into existing circuits originally designed for slower logic families.
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