MC10H640FNG

Overview

The MC10H640FNG is a clock driver designed for 68030 and 68040 microprocessors. It accepts TTL or PECL inputs and provides six TTL outputs with internal divide-by-two and divide-by-four stages. The device operates on a single +5.0 V supply (4.75 V to 5.25 V) and supports maximum input frequencies up to 135 MHz. Propagation delay ranges from 4.0 ns to 6.3 ns depending on the output stage, with within-device skew limited to 0.5 ns. It features an asynchronous reset function and is housed in a 28-lead PLCC package.

Feature Summary

• Generates clocks for 68030/040 MPUs with guaranteed part-to-part and within-part skew.
• Accepts both TTL and PECL (ECL referenced to +5.0 V) input clock sources.
• Includes internal divide-by-two and divide-by-four stages for duty cycle control.
• Asynchronous reset forces all Q outputs LOW and all Q-bar outputs HIGH.

Applications

• Clock generation for Motorola 68030 microprocessors.
• Clock generation for Motorola 68040 microprocessors.
• High-speed clock distribution systems requiring low skew.

Procurement Notes

Verify component authenticity through authorized channels as counterfeit risks exist for legacy logic ICs. Confirm RoHS compliance status and moisture sensitivity level (MSL 3) prior to surface mount assembly. Check for specific ordering suffixes if tube packaging is required instead of standard bulk options.

Selection Notes

Select this component when interfacing differential ECL/PECL signals to TTL loads for 68030/040 MPU architectures. Ensure load capacitance remains within specified limits (e.g., 10 pF to 50 pF) to maintain duty cycle accuracy at high frequencies. Verify that the 28-PLCC footprint matches the target PCB layout constraints.

Part Context

This device belongs to the MC10H series of high-speed ECL/TTL logic components manufactured by onsemi. It is specifically engineered to meet the strict timing requirements of older 32-bit microprocessor families. The FNG suffix indicates a lead-free, halogen-free PLCC-28 package compliant with RoHS directives.

Replacement Considerations

Direct pin-compatible replacements are not explicitly listed in the provided documentation. Evaluate other devices within the MC10H64x family or general-purpose clock drivers that support PECL/TTL translation and match the 28-PLCC form factor.

FAQ

How does the device handle open ECL inputs?

The H640 includes circuitry to force a stable state if both sides of the ECL input differential pair are left open. In this scenario, the DE side is pulled LOW and DE_bar goes HIGH.

What is the maximum operating frequency?

The maximum input frequency is 135 MHz under standard test conditions with a 25 pF load capacitance.

How is the power-up state managed?

The device is designed so that the positive edges of the ÷2 and ÷4 outputs are synchronized at power up.