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MC74HC390ADTR2G is listed in the Counter Dividers range at ChipApex. The manufacturer field lists onsemi. Its product description is IC DECADE COUNT DL 4BIT 16TSSOP. Review the specifications below when checking this part for your BOM.
The MC74HC390ADTR2G is a high-performance silicon-gate CMOS dual 4-stage binary ripple counter with divide-by-two and divide-by-five sections. It operates within a supply voltage range of 2.0 V to 6.0 V and supports an operating temperature from -55°C to +125°C. The device features asynchronous reset inputs for each counter section and outputs directly interface to CMOS, NMOS, and TTL loads. Maximum clock frequencies reach up to 50 MHz at 6.0 V, with propagation delays varying by configuration and voltage.
Verify the specific package suffix 'DT' corresponds to the TSSOP-16 form factor required for your PCB layout. Confirm that the ordering code includes the 'G' designation to ensure compliance with lead-free and RoHS standards. Cross-reference the manufacturer's latest datasheet revision to validate electrical parameters against your system requirements before finalizing procurement.
Select this component when a dual-counter solution with independent clock inputs is necessary. Ensure the application voltage falls between 2.0 V and 6.0 V to maintain specified performance levels. Consider the ripple counter architecture's decoding spikes if the outputs are used as clocks; gating with the main clock may be required for stable operation in synchronous designs.
This part belongs to the MC74HC390A series, which maintains pinout compatibility with LS390 devices. It is manufactured using high-performance silicon-gate CMOS technology. The device is available in multiple packages including SOIC-16, QFN16, and TSSOP-16, with the ADTR2G variant specifically denoting the TSSOP-16 surface-mount package.
MC74HC390ADG
For BCD counting, connect output QA to the Clock B input. This configuration creates a decade divider with BCD output where QA serves as the least significant bit.
The internal flip-flops are triggered by high-to-low transitions of the respective clock inputs (Clock A or Clock B).
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