MC88916EG80R2

Overview

The MC88916EG80R2 is a low skew CMOS PLL clock driver designed for CISC microprocessor or single processor RISC systems. It utilizes phase-locked loop technology to lock outputs onto an input reference clock, providing distribution for the MC68/EC/LC030/040 family. The device features six total outputs: three Q outputs (Q0–Q2) with less than 500ps skew, one inverted Q3 output, a 2X_Q output running at twice the system frequency, and a Q/2 output. It operates on a 4.5V to 5.5V supply in a 20-SOIC package.

Feature Summary

• PLL-based clock distribution with <500ps skew between Q0-Q2 outputs
• Integrated processor reset function via RST_IN/RST_OUT(LOCK) pins
• Six outputs including Q0-Q2, inverted Q3, 2X_Q, and Q/2
• CMOS/TTL compatible inputs with ±36mA drive capability

Applications

• MC68030 Microprocessor Clock Distribution
• 33MHz and 40MHz MC68040 Microprocessor Systems
• Single Processor RISC System Clocking

Procurement Notes

Verify the specific suffix 'EG80R2' against official manufacturer documentation to confirm exact speed grade and packaging variations. Ensure compatibility with the required 5V logic levels and check if the 2X_Q output meets duty cycle requirements for specific target processors like the 68040 PCLK input.

Selection Notes

Select this component when driving MC68030 or 68040 processors requiring low skew clock distribution. The DW80 variant supports up to 80MHz on the 2X_Q output. Use the 88920 if strict duty cycle compliance is needed for lower frequency 68040 PCLK inputs, as the 88916 2X_Q may not meet those specific requirements.

Part Context

Originally manufactured by Motorola, this part was later acquired by Freescale Semiconductor and subsequently Integrated Device Technology (IDT). Renesas Electronics Corporation now lists this legacy timing solution. The device belongs to the IDT Low Skew CMOS PLL Clock Driver family.

Replacement Considerations

For 68040 PCLK applications requiring stricter duty cycles, consider the MC88920. For general replacement, verify pinout compatibility with other MC88916 variants such as the MC88916DW70 or MC88916DW80.

FAQ

What is the maximum operating frequency of the 2X_Q output?

The MC88916DW80 grade supports a maximum 2X_Q frequency of 80 MHz.

How does the RST_OUT pin function during power-up?

If RST_IN is held high, RST_OUT stays low until phase-lock is achieved, then goes high impedance after 1024 Q cycles.

Can the MC88916 drive TTL inputs?

Yes, all inputs are TTL-level compatible, and outputs provide ±36mA drive suitable for CMOS or TTL loads.