MC88920DW

Overview

The MC88920 is a low skew CMOS PLL clock driver designed for CISC and RISC microprocessor systems. It utilizes phase-locked loop technology to lock outputs onto an input reference, providing distribution with minimal delay. The device features six total outputs: three Q outputs (Q0-Q2), one inverted Q3 output, one Q/2 output, and one 2X_Q output running at double the system frequency. It supports a maximum operating frequency of 50 MHz on the 2X_Q output and 25 MHz on the Q outputs. The component operates within a 4.5V to 5.5V supply range and is housed in a 20-SOIC package.

Feature Summary

• Integrates a PLL to distribute a single clock input to multiple locations with essentially zero delay and low skew.
• Provides six outputs including a 2X_Q output specifically meeting 68040 PCLK requirements and three Q outputs with <500ps skew.
• Includes dedicated RST_IN/RST_OUT(LOCK) pins to manage processor reset sequences and indicate phase-lock status.
• Features a special power-down mode via the MR pin that resets specific outputs while allowing others to remain operational.

Applications

• Clock distribution for MC68/EC/LC030/040 microprocessor families
• Single processor RISC systems requiring precise timing alignment
• Board-level clock generation where low skew between multiple loads is critical

Procurement Notes

Verify the manufacturing source, as the part was originally produced by Motorola and later associated with Freescale Semiconductor before NXP acquisition. Confirm RoHS compliance status, as older production runs may not meet current environmental standards. Ensure the 20-SOIC package dimensions match the design footprint, specifically noting the 7.50mm width. Check for availability of the specific suffix 'DW' which denotes the plastic SOIC package variant.

Selection Notes

Select this component when a fixed 2X multiplication from the SYNC input to the VCO is required without external feedback loops. It is suitable for applications needing a dedicated high-frequency output for processors like the 68040. Consider the internal fixed relationship between inputs and outputs; if variable frequency multiplication is needed, this fixed-ratio architecture may be restrictive. Ensure the system can accommodate the recommended analog loop filter components for stable operation.

Part Context

The MC88920 belongs to the MC88 series of timing solutions, originally developed by Motorola. It serves as a specialized clock buffer and driver for high-performance microprocessors prevalent in the mid-1990s. The device addresses the need for synchronized clock distribution in complex digital systems where propagation delay variations could cause timing violations.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Due to the specific fixed frequency ratios and legacy processor compatibility (MC68040), direct replacements may require redesigning the clock tree or verifying functional equivalence of the PLL characteristics and output drive strengths.