MC88LV926DWR2

Overview

The MC88LV926DWR2 is a low-skew CMOS PLL clock driver designed for CISC/RISC microprocessor systems. It features a single circuit with a 1:6 input-to-output ratio, operating at a maximum frequency of 66 MHz on the 2X_Q output and 33 MHz on Q0–Q3 outputs. Powered by a 3V to 5.25V supply, it provides five outputs (Q0–Q3, 2X_Q, CLKEN) with ±36mA drive capability. The device includes an integrated reset function via RST_IN/RST_OUT(LOCK) pins, specifically tailored for the Motorola 68030/040/060 processor families. It utilizes internal feedback for fixed 2X multiplication and operates within a commercial temperature range of 0°C to 70°C in a 20-SOIC package.

Feature Summary

• PLL-based clock distribution with low skew (<500ps between Q0-Q2 rising edges)
• Integrated reset logic for 68030/040/060 processors with phase-lock indication
• Dual voltage operation supporting 3.3V and 5.0V supplies
• Test mode pin (PLL_EN) allows static testing without frequency limitations

Applications

• Clock distribution for Motorola 68060 microprocessors
• Single processor RISC system clock generation
• CISC microprocessor bus clocking requiring half-speed CLKEN signals

Procurement Notes

The MC88LV926DWR2 is listed as a discontinued product by NXP USA Inc. Verification of availability should focus on surplus or secondary market sources rather than direct manufacturer allocation. Confirm RoHS compliance status, as the component may not meet current environmental standards. Ensure the specific suffix DWR2 matches the required 20-SOIC plastic package dimensions.

Selection Notes

Select this component when designing for legacy Motorola 68K family processors requiring precise phase alignment and integrated reset sequencing. Verify that the 66MHz maximum frequency meets system requirements. Note that the SYNC input frequency range is limited to 5MHz up to Fmax(2X_Q)/4. Ensure external loop filter components match the recommended values to maintain jitter performance and lock time specifications.

Part Context

This part belongs to the MC88 series of timing solutions originally developed by Motorola and later acquired by NXP. It is distinct from general-purpose clock buffers due to its specialized integration of PLL functionality and processor-specific reset control. The 'LV' designation indicates low-voltage compatibility, while 'DWR2' specifies the wide SOIC package and tape-and-reel packaging format.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Due to the discontinued status and specialized interface with legacy 68K processors, direct pin-compatible replacements may require careful evaluation of reset timing and voltage level compatibility.