MCP6S92-E/P

Overview

The MCP6S92-E/P is a dual-channel analog programmable gain amplifier (PGA) from Microchip Technology, housed in an 8-pin PDIP package. It supports gains from +1 V/V to +32 V/V via SPI control and features rail-to-rail input/output operation on a single supply of 2.5V to 5.5V. The device offers a typical bandwidth of 1 to 18 MHz, low noise density of 10 nV/√Hz at 10 kHz, and operates within an extended temperature range of -40°C to +125°C.

Feature Summary

• Dual-channel architecture with internal multiplexer for selecting between two analog inputs
• SPI-controlled gain configuration ranging from +1 V/V to +32 V/V
• Rail-to-rail input and output capability optimized for single-supply applications
• Low offset voltage mismatch between channels and low quiescent current consumption

Applications

• A/D converter driver circuits
• Multiplexed analog signal acquisition systems
• Industrial instrumentation front-ends
• Medical instrumentation signal conditioning

Procurement Notes

Verify the specific suffix 'E/P' corresponds to the PDIP package and industrial temperature grade (-40°C to +125°C). Confirm that the VREF pin is internally tied to VSS for this variant, which impacts power supply rejection ratio specifications compared to other family members. Ensure compatibility with standard SPI logic levels for your microcontroller interface.

Selection Notes

Select the MCP6S92-E/P when dual independent channel amplification with digital gain control is required. It is suitable for applications needing flexible performance or multiple inputs without external discrete components. Consider the 8-pin PDIP package for through-hole prototyping or manufacturing requirements where surface mount options are not preferred.

Part Context

This component belongs to the MCP6S91/2/3 family of single-ended, rail-to-rail I/O, low-gain PGAs. While the MCP6S91 is a single-channel device and the MCP6S93 uses a 10-pin MSOP package, the MCP6S92 specifically provides two channels in an 8-pin form factor. All variants share similar electrical characteristics but differ in channel count and physical packaging.

Replacement Considerations

MCP6S91-E/P (Single-channel equivalent)

FAQ

How does the MCP6S92 handle the VREF pin?

For the MCP6S92, the VREF pin is internally tied to VSS. This configuration means the Power Supply Rejection Ratio (PSRR) specification describes PSRR+ only, and it is recommended to tie the VSS pin directly to ground to avoid noise problems.

What is the maximum SPI clock frequency?

The maximum SCK frequency is 10 MHz when operating at VDD = 5V. In daisy-chain configurations, the maximum frequency is lower, approximately 5.8 MHz, due to propagation delay and setup time constraints.